메뉴 건너뛰기




Volumn 5, Issue , 1998, Pages 3073-3076

Loop scheduling algorithms for power reduction

Author keywords

[No Author keywords available]

Indexed keywords

FUNCTIONAL UNITS; LOOP PIPELINING; LOOP SCHEDULING; LOOP SCHEDULING ALGORITHMS; POWER REDUCTIONS; SCHEDULE LENGTH; SCIENTIFIC APPLICATIONS; TRANSITION ACTIVITY;

EID: 0031619415     PISSN: 15206149     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICASSP.1998.678175     Document Type: Conference Paper
Times cited : (9)

References (10)
  • 5
    • 33746763910 scopus 로고
    • Retiming synchronous circuitry
    • Charles E. Leiserson, and James B. Saxe, "Retiming Synchronous Circuitry", Algorithmica, 1991, 6:5-35
    • (1991) Algorithmica , vol.6 , pp. 5-35
    • Leiserson, C.E.1    Saxe, J.B.2
  • 8
    • 0029518878 scopus 로고
    • Push-up scheduling: Optimal polynomial-time resource constrained scheduling for multi-dimensional applications
    • San Jose, CA, November
    • N. Passos and E. H.-M. Sha, "Push-Up Scheduling: Optimal Polynomial-Time Resource Constrained Scheduling for Multi-Dimensional Applications", in Proc. IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, November 1995, pp. 588-591
    • (1995) Proc. IEEE/ACM International Conference on Computer-Aided Design , pp. 588-591
    • Passos, N.1    Sha, E.H.-M.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.