Assisting network intrusion detection with reconfigurable hardware

IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings

Volumn 2002-January, Issue , 2002, Pages 111-120

  Hutchings, B L ^a   Franklin, R ^a   Carver, D ^a  

^a Department of Electrical and Computer Engineering   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTERS; INTRUSION DETECTION; LOGIC SYNTHESIS; MERCURY (METAL); OPEN SOURCE SOFTWARE; PATTERN MATCHING; RECONFIGURABLE HARDWARE;

BIT STREAM; FPGA CIRCUITS; INCOMING PACKETS; MODULE GENERATOR; NETWORK INTRUSION DETECTION; NETWORK INTRUSION DETECTION SYSTEMS; REGULAR EXPRESSIONS; STRING MATCHING;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 84950138443     PISSN: 10823409     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPGA.2002.1106666     Document Type: Conference Paper

References (11)

1. P. Bellows and B. L. Hutchings. JHDL - an HDL for reconfigurable systems. In J. M. Arnold and K. L. Pocek, editors, Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, pages 175-184, Napa, CA, April 1998.
2. C. J. Coit, S. Staniford, and J. McAlerney. Toward faster string matching for intrusion detection or exceeding the speed of snort. In DARPA Information Survivability Conference and Exposition II, 2001 Proceedings, volume 1, pages 367-373, 2001.
3. W. Culbertson, R. Amerson, R. Carter, P. Kuekes, and G. Snider. The Teramac configurable custom computer. In J. Schewel, editor, Proceedings of the International Society of Optical Engineering (SPIE). Field Programmable Gate Arrays (FPGAs) for Fast Board Development and Reconfigurable Computing., pages 201-209, Philadephia, PA, October 1995.
4. P. W. Foulk. Data-folding in SRAM configurable FP-GAs. In D. A. Buell and K. L. Pocek, editors, Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, pages 163-171, Napa, CA, April 1993.
5. B. Gunther, G. Milne, and L. Narasimhan. Assessing document relevance with run-time reconfigurable machines. In J. Arnold and K. L. Pocek, editors, Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, pages 10-17, Napa, CA, April 1996.
6. S. Hemmert and B. L. Hutchings. An applicationspecific compiler for high-speed image morphology. In J. M. Arnold and K. L. Pocek, editors, Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, pages to-appear, Napa, CA, April 2001.
7. B. Hutchings, P. Bellows, J. Hawkins, S. Hemmert, B. Nelson, and M. Rytting. A cad suite for highperformance fpga design. In K. L. Pocek and J. M. Arnold, editors, Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, page n/a, Napa, CA, April 1999. IEEE Computer Society, IEEE.
8. D. P. Lopresti. Rapid implementation of a genetic sequence comparator using field-programmable gate arrays. In C. Sequin, editor, Advanced Research in VLSI: Proceedings of the 1991 University of California/Santa Cruz Conference, pages 138-152, Santa Cruz, CA, March 1991.
9. D. V. Pryor, M. R. Thistle, and N. Shirazi. Text searching on Splash 2. In D. A. Buell and K. L. Pocek, editors, Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, pages 172-177, Napa, CA, April 1993.
10. Martin Roesch. Snort - lightweight intrusion detection for networks. In 13th Systems Administration Conference, LISA'99, Seattle, WA, November 1999. www.usenix.org/events/lisa99/full-papers/roesch/roesch-html/.
11. R. Sidhu and V. K. Prasanna. Fast regular expression matching using fpgas. In J. M. Arnold and K. L. Pocek, editors, Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, pages toappear, Napa, CA, April 2001.