A dynamically reconfigurable FPGA-based content addressable memory for internet protocol characterization

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1896, Issue , 2000, Pages 19-28

  Ditmar, Johan ^a   Torkelsson, Kjell ^a   Jantsch, Axel ^b  

^a ERICSSON RADIO SYSTEMS AB   (Sweden)

^b ROYAL INSTITUTE OF TECHNOLOGY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

ASSOCIATIVE STORAGE; CLASSIFICATION (OF INFORMATION); COMPUTATION THEORY; DYNAMIC MODELS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); MEMORY ARCHITECTURE; RECONFIGURABLE ARCHITECTURES; RECONFIGURABLE HARDWARE;

DYNAMIC RE-CONFIGURATION; DYNAMICALLY RECONFIGURABLE FPGA; IP PACKETS; NOVEL ARCHITECTURE; RECONFIGURABLE; SEARCH WORDS;

INTERNET PROTOCOLS;

EID: 33746865224     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-44614-1_3     Document Type: Conference Paper

References (10)

1. [1] A. McEwan, J. Saul, A. Bayley, “A High Speed Reconfigurable Firewall Based On Parameterizable FPGA-based Content Addressable Memories”, Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA), 1999.
2. [2] M. Defossez, “Content Addressable Memory (CAM) in ATM applications”, Xilinx Application Note 202, 1999.
3. [3] J. Brelet, B. New, “Designing Flexible, Fast CAMs with Virtex Slices”, Xilinx Application Note 203, 1999.
4. [4] J. Brelet, “Using Block SelectRAM+ for High-Performance Read/Write CAMs”, Xilinx Application Note 204, 1999.
5. [5] S. Deering, R. Hinden, Internet Protocol, Ver. 6 Specification, RFC 2460, 1998.
6. [6] M. Mansour, A. Kayssi, “FPGA-based Internet Protocol Version 6 Router”, Proc. of IEEE International Conference on Computer Design, p. 334, vol. 2, 1998.
7. [7] S. Guccione, D. Levi, “Run-Time Parameterizable Cores”, Proceedings of the 9th International Workshop of Field Programmable Logic and Applications FPL ‘99, p. 215, Springer Lecture Notes in Computer Science, 1998.
8. [8] Xilinx Inc, “JBits Xilinx Reconfigurable Computing Platform”, JBits 2.1 Tutorial, 1999.
9. [9] A.J. McAuley, P. Francis, “Fast Routing Table Lookup Using CAMs”, Proceedings of IEEE Infocom ‘93, p. 1382, 1993.
10. [10] S. V. Kartalopoulos, “An Associative RAM-based CAM and Its Application to BroadBand Communiactions Systems”, IEEE Transactions on Neural Networks, p. 1036, vol. 9, 1998.