-
1
-
-
0026139605
-
A formal approach to the scheduling problem in high level synthesis
-
April
-
C.-T. Hwang, J.-H. Lee, Y.-C. Hsu, "A Formal Approach to the Scheduling Problem in High Level Synthesis", IEEE Transactions on Computer-Aided Design, Vol. 10, No. 4, April 1991, pp. 464-475.
-
(1991)
IEEE Transactions on Computer-Aided Design
, vol.10
, Issue.4
, pp. 464-475
-
-
Hwang, C.-T.1
Lee, J.-H.2
Hsu, Y.-C.3
-
2
-
-
0031620595
-
Complexity of scheduling in high-level synthesis
-
C. A. Mandal, P. P. Chakrabarti, S. Ghoste, " Complexity of Scheduling in High-Level Synthesis", VLSI systems Design, Vol. 7, No. 4, 1998, pp. 337-346.
-
(1998)
VLSI Systems Design
, vol.7
, Issue.4
, pp. 337-346
-
-
Mandal, C.A.1
Chakrabarti, P.P.2
Ghoste, S.3
-
3
-
-
0003558118
-
-
Kluwer Academic Publishers The Netherlands
-
D. Gajski, N. Dutt, A. We, S. Lin, "High-Level Synthesis Introduction to Chip and System Design", Kluwer Academic Publishers, The Netherlands, 1994.
-
(1994)
High-level Synthesis Introduction to Chip and System Design
-
-
Gajski, D.1
Dutt, N.2
We, A.3
Lin, S.4
-
4
-
-
0027680865
-
FAMOS: An efficient scheduling algorithm for high-level synthesis
-
October
-
In-Cheol Park, Chong-Min Kyung, "FAMOS: An Efficient Scheduling Algorithm for High-Level Synthesis", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 12, No. 10, October 1993, pp. 1437-1448.
-
(1993)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, vol.12
, Issue.10
, pp. 1437-1448
-
-
Park, I.-C.1
Kyung, C.-M.2
-
5
-
-
0023983163
-
SEHWA, A software package for synthesis of pipelines from behavioral specifications
-
March
-
N. Park, A. C. Parker: "SEHWA, "A Software Package for Synthesis of Pipelines from Behavioral Specifications", IEEE Transactions on Computer-Aided Design, Vol. 7, No. 3, March 1988, pp. 356-370.
-
(1988)
IEEE Transactions on Computer-Aided Design
, vol.7
, Issue.3
, pp. 356-370
-
-
Park, N.1
Parker, A.C.2
-
6
-
-
0000577173
-
SALSA a new approach to scheduling with timing constraints
-
August
-
J. A. Nestor, G. Krishnamoorthy: SALSA, "A New Approach to Scheduling with Timing Constraints", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 12, No. 8, August 1993, pp. 1107-1122.
-
(1993)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, vol.12
, Issue.8
, pp. 1107-1122
-
-
Nestor, J.A.1
Krishnamoorthy, G.2
-
7
-
-
0024944691
-
Algorithms for high-level synthesis
-
Dec.
-
P. G. Paulin, J. Knight, "Algorithms for High-Level Synthesis", IEEE Design & Test of Computers, Vol. 6, No. 6, Dec. 1989, pp. 18-31.
-
(1989)
IEEE Design & Test of Computers
, vol.6
, Issue.6
, pp. 18-31
-
-
Paulin, P.G.1
Knight, J.2
-
8
-
-
0024682923
-
Force-directed scheduling for the behavioral synthesis of ASIC's
-
June
-
P. G. Paulin, J. P. Knight, "Force-Directed Scheduling for the Behavioral Synthesis of ASIC's", IEEE Transactions on Computer-Aided Design, Vol. 8, No. 6, June 1989, pp. 661-679.
-
(1989)
IEEE Transactions on Computer-Aided Design
, vol.8
, Issue.6
, pp. 661-679
-
-
Paulin, P.G.1
Knight, J.P.2
-
9
-
-
0025791177
-
Path-based scheduling for synthesis
-
Jan.
-
R. Camposano, "Path-Based Scheduling for Synthesis", IEEE Transactions on Computer-Aided Design, Vol. 10, No. 1, Jan. 1991, pp. 85-93.
-
(1991)
IEEE Transactions on Computer-Aided Design
, vol.10
, Issue.1
, pp. 85-93
-
-
Camposano, R.1
-
10
-
-
0029322673
-
Introduction to the scheduling problem
-
summer
-
R. A. Walker, S. Chaudhuri, "Introduction to the scheduling problem", IEEE Design & Test of Computers, Vol. 12, No. 2, summer 1995, pp.60-69.
-
(1995)
IEEE Design & Test of Computers
, vol.12
, Issue.2
, pp. 60-69
-
-
Walker, R.A.1
Chaudhuri, S.2
-
11
-
-
0030686690
-
Cone-based clustering heuristic for list-scheduling algorithms
-
Paris, France, IEEE Computer Society, March
-
S. Govindarajan, R. Vemuri, " Cone-Based Clustering Heuristic for List-Scheduling Algorithms", Proceedings of European Design & Test Conference (ED&TC), Paris, France, IEEE Computer Society, March 1997, pp. 456-462.
-
(1997)
Proceedings of European Design & Test Conference (ED&TC)
, pp. 456-462
-
-
Govindarajan, S.1
Vemuri, R.2
-
13
-
-
0032640514
-
A circuit-driven design methodology for video signal-processing datapath elements
-
June
-
S. Dutta, W. Wolf, "A Circuit-Driven Design Methodology for Video Signal-Processing Datapath Elements", IEEE Transactions on VLSI Systems, Vol. 7, No. 2, June 1999, pp. 229-240.
-
(1999)
IEEE Transactions on VLSI Systems
, vol.7
, Issue.2
, pp. 229-240
-
-
Dutta, S.1
Wolf, W.2
-
14
-
-
84949660736
-
Design space exploration scheme for high-level synthesis systems
-
Ostrava, Czech Republic, April
-
A. M. Sllame, V. Drabek, "Design Space Exploration Scheme for High-Level Synthesis Systems", Proceedings of 36th International Conference Modelling and Simulation of Systems MOSIS'02, Ostrava, Czech Republic, April 2002, pp. 305-312.
-
(2002)
Proceedings of 36th International Conference Modelling and Simulation of Systems MOSIS'02
, pp. 305-312
-
-
Sllame, A.M.1
Drabek, V.2
-
16
-
-
0029357329
-
Datapath synthesis using a problem-space genetic algorithm
-
August
-
M. K. Dhodhi, F. H. Hielscher, R. H. Storer, J. Bhasker, "Datapath Synthesis Using a Problem-Space Genetic Algorithm", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 14, No. 8, August 1995, pp. 934-944.
-
(1995)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, vol.14
, Issue.8
, pp. 934-944
-
-
Dhodhi, M.K.1
Hielscher, F.H.2
Storer, R.H.3
Bhasker, J.4
-
17
-
-
0026903189
-
Predicting system-level area and delay for pipelined and nonpipelined designs
-
August
-
R. Jain, A. C. Parker, N. Park, "Predicting System-Level Area and Delay for Pipelined and Nonpipelined Designs", IEEE Transactions on Computer-Aided Design, Vol. 11, No. 8, August 1992, pp. 955-965.
-
(1992)
IEEE Transactions on Computer-Aided Design
, vol.11
, Issue.8
, pp. 955-965
-
-
Jain, R.1
Parker, A.C.2
Park, N.3
-
18
-
-
84944131847
-
An evolutionary-based algorithm to the module selection process in high-level synthesis
-
Brno, Czech Republic, June 2002
-
A. M. Sllame, L. Sekanina, "An Evolutionary-Based Algorithm to the Module Selection Process in High-Level Synthesis", Proceedings of Mendel 2002-8th International Conference on Soft Computing, Brno, Czech Republic, June 2002, pp. 87-92.
-
Proceedings of Mendel 2002-8th International Conference on Soft Computing
, pp. 87-92
-
-
Sllame, A.M.1
Sekanina, L.2
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