메뉴 건너뛰기




Volumn 1536, Issue , 1998, Pages 239-275

Deductive verification of modular systems

Author keywords

[No Author keywords available]

Indexed keywords

ARTIFICIAL INTELLIGENCE; COMPUTER SCIENCE; COMPUTERS;

EID: 84949233486     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-49213-5_9     Document Type: Conference Paper
Times cited : (15)

References (29)
  • 2
    • 0024144406 scopus 로고
    • The existence of refinement mappings
    • IEEE Computer Society Press
    • M. Abadi and L. Lamport. The existence of refinement mappings. In Proc. 3rd IEEE Symp. Logic in Comp. Sci.., pages 165-175. IEEE Computer Society Press, 1988.
    • (1988) Proc. 3Rd IEEE Symp. Logic in Comp. Sci. , pp. 165-175
    • Abadi, M.1    Lamport, L.2
  • 6
    • 85034858735 scopus 로고
    • Hierarchical development of concurrent systems in a temporal logic framework
    • Springer-Verlag
    • H. Barringer and R. Kuiper. Hierarchical development of concurrent systems in a temporal logic framework. In Seminar on Concurrency, vol. 197 of LNCS, pages 35-61. Springer-Verlag, 1984.
    • (1984) Seminar on Concurrency , vol.197 , pp. 35-61
    • Barringer, H.1    Kuiper, R.2
  • 9
    • 23544466524 scopus 로고    scopus 로고
    • Deductive verification of real-time systems using STeP
    • Springer-Verlag,May
    • N.S. Bjørner, Z. Manna, H.B. Sipma, and T.E. Uribe. Deductive verification of real-time systems using STeP. In 4th Intl. AMAST Workshop on Real-Time Systems, vol. 1231 of LNCS, pages 22-43. Springer-Verlag, May 1997.
    • 4Th , vol.1231 , pp. 22-43
    • Bjørner, N.S.1    Manna, Z.2    Sipma, H.B.3    Uribe, T.E.4
  • 10
    • 9644253660 scopus 로고
    • PhD thesis, Computer Science Department, Stanford University, Stanford, California, Tech. Report STAN-CS-TR-94-1522
    • E.S. Chang. Compositional Verification of Reactive and Real-Time Systems. PhD thesis, Computer Science Department, Stanford University, Stanford, California, 1993. Tech. Report STAN-CS-TR-94-1522.
    • (1993) Compositional Verification of Reactive and Real-Time Systems
    • Chang, E.S.1
  • 12
    • 34548795625 scopus 로고
    • Verification of vlsi circuits using 1p
    • In G.J. Milne, editor,, Elsevier Science Publishers B.V. (North Holland)
    • S. Garland, J. Guttag, and J. Staunstrup. Verification of vlsi circuits using 1p. In G.J. Milne, editor, The Fusion of Hardware Design and Verification, pages 329-345. Elsevier Science Publishers B.V. (North Holland), 1988.
    • (1988) The Fusion of Hardware Design and Verification , pp. 329-345
    • Garland, S.1    Guttag, J.2    Staunstrup, J.3
  • 13
    • 0028427381 scopus 로고
    • Model checking and modular verification
    • O. Grumberg and D.E. Long. Model checking and modular verification. ACM Trans. Prog. Lang. Sys., 16(3):843-871, May 1994.
    • (1994) ACM Trans. Prog. Lang. Sys , vol.16 , Issue.3 , pp. 843-871
    • Grumberg, O.1    Long, D.E.2
  • 14
    • 84976735431 scopus 로고
    • Tentative steps toward a development method for interfering programs
    • C. Jones. Tentative steps toward a development method for interfering programs. ACM TOPLAS, 5(4):596-619, 1983.
    • (1983) ACM TOPLAS , vol.5 , Issue.4 , pp. 596-619
    • Jones, C.1
  • 16
    • 84886699020 scopus 로고    scopus 로고
    • Temporal verification of simulation and refinement
    • In J.W. de Bakker, W.P. de Roever, and G. Rosenberg, editors, of LNCS, Springer-Verlag
    • Y. Kesten, Z. Manna, and A. Pnueli. Temporal verification of simulation and refinement. In J.W. de Bakker, W.P. de Roever, and G. Rosenberg, editors, A Decade of Concurrency, vol. 803 of LNCS, pages 273-346. Springer-Verlag, 1994.
    • A Decade of Concurrency , vol.803 , pp. 273-346
    • Kesten, Y.1    Manna, Z.2    Pnueli, A.3
  • 17
    • 85031892754 scopus 로고
    • Hierarchical correctness proofs for distributed algorithms
    • ACM Press
    • N.A. Lynch and M.R. Tuttle. Hierarchical correctness proofs for distributed algorithms. In Proceedings of the Sixth Annual Symposium on Principles of Distributed Computing, pages 137-151. ACM Press, 1987.
    • (1987) Proceedings of the Sixth Annual , pp. 137-151
    • Lynch, N.A.1    Tuttle, M.R.2
  • 18
    • 0001383866 scopus 로고
    • An introduction to input/output automata
    • N.A. Lynch and M. Tuttle. An introduction to input/output automata. CWI-Quarterly, 2(3):219-246, 1989.
    • (1989) Cwi-Quarterly , vol.2 , Issue.3 , pp. 219-246
    • Lynch, N.A.1    Tuttle, M.2
  • 21
    • 84995731256 scopus 로고
    • Temporal verification diagrams
    • In M. Hagiya and J.C. Mitchell, editors
    • Z. Manna and A. Pnueli. Temporal verification diagrams. In M. Hagiya and J.C. Mitchell, editors, Proc. International Symposium, on Theoretical Aspects of Computer Software, vol. 789 of LNCS, pages 726-765. Springer-Verlag, 1994.
    • (1994) Proc. International Symposium, on Theoretical Aspects Of , vol.789 , pp. 726-765
    • Manna, Z.1    Pnueli, A.2
  • 24
    • 0038357007 scopus 로고
    • In transition from global to modular temporal reasoning about programs
    • In K.R. Apt, editor, Springer-Verlag
    • A. Pnueli. In transition from global to modular temporal reasoning about programs. In K.R. Apt, editor, Logics and Models of Concurrent Systems, sub-series F: Computer and System Science, pages 123-144. Springer-Verlag, 1985.
    • (1985) Logics and Models of Concurrent , pp. 123-144
    • Pnueli, A.1
  • 26
    • 84887090955 scopus 로고    scopus 로고
    • Technical report, Computer Science Laboratory, SRI International, Menlo Park, California, December
    • N. Shankar. A lazy approach to compositional verification. Technical report, Computer Science Laboratory, SRI International, Menlo Park, California, December 1993.
    • A Lazy Approach to Compositional Verification , pp. 1993
    • Shankar, N.1
  • 28
    • 84949279769 scopus 로고    scopus 로고
    • J. Staunstrup. A Formal Approach to Hardware Design. Kluwer Academic Publishers, 1994.
    • Staunstrup, J.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.