Deductive verification of real-time systems using STeP

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1231, Issue , 1997, Pages 22-43

  BjØrner, Nikolaj S ^a   Manna, Zohar ^a   Sipma, Henny B ^a   Uribe, Tomás E ^a  

^a Stanford University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTERACTIVE COMPUTER SYSTEMS; TEMPORAL LOGIC;

AUTOMATIC INVARIANT GENERATIONS; DEDUCTIVE VERIFICATION; LINEAR TIME TEMPORAL LOGIC; MECHANICAL VERIFICATION; MODULAR FRAMEWORK; STANFORD; TEMPORAL PROPERTY; TRANSITION SYSTEM;

REAL TIME SYSTEMS;

EID: 23544466524     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-63010-4_3     Document Type: Conference Paper

References (35)

1. J. Armstrong and L. Barroca. Specification and verification of reactive system behaviour: The railroad crossing example. Real-Time Systems, 10:143178, 1996.
2. R. Alur and D.L. Dill. A theory of timed automata. Theor. Comp. Sei., 126:183-235, 1994.
3. M. Abadi and L. Lamport. An old-fashioned recipe for real time. In Proceedings of the REX Workshop "Real-Time: Theory in Practice", volume 600 of LNCS, pages 1-27. Springer-Verlag, 1992.
4. N.S. Bjorner, A. Browne, E. Chang, M. Colon, A. Kapur, Z. Manna, H.B. Sipma, and Т.Е. Uribe. STeP: The Stanford Temporal Prover, User's Manual. Technical Report STAN-CS-TR-95-1562, Computer Science Department, Stanford University, November 1995.
5. th Intl. Conference on Computer Aided Verification, volume 1102 of LNCS, pages 415-418. Springer-Verlag, July 1996.
6. N.S. Bjørner, A. Browne, and Z. Manna. Automatic generation of invariants and intermediate assertions. Theor. Comp. Sei., 173(l):49-87, February 1997.
7. J. Bengtsson, K.G. Larson, F. Larsson, P. Pettersson, and W. Yi. Uppaal - a Tool Suite for Automatic Verification of Real-Time Systems. In Proc. of the 4th DIM ACS Workshop on Verification and Control of Hybrid Systems, volume 1066 of LNCS, pages 232-243, 1995.
8. th Intl. Conference on Computer Aided Verification, volume 1102 of LNCS, pages 323-335. Springer-Verlag, 1996.
9. A. Browne, Z. Manna, and H.B. Sipma. Generalized temporal verification diagrams. In 15th Conference on the Foundations of Software Technology and Theoretical Computer Science, volume 1026 of LNCS, pages 484-498, 1995.
10. N.S. Bjørner, M.E. Stickel, and Т.Е. Uribe. A practical combination of first-order reasoning and decision procedures. In 14th Intl. Conference on Automated Deduction, LNCS. Springer-Verlag, July 1997. To appear.
11. S. Campos and E. Clarke. Real-time symbolic model checking for discrete time models. In Theories and Experiences for Real- Time System Development., AMAST. World Scientific Publishing Company, 1995.
12. E.S. Chang. Compositional Verification of Reactive and Real-Time Systems. PhD thesis, Computer Science Department, Stanford University, Stanford, California, 1993. Tech. Report STAN-CS-TR-94-1522.
13. Z. Chaochen, C.A.R Hoare, and A.P. Ravn. A calculus of durations. Information Processing Letters, 40(5):269-276, 1992.
14. E.S. Chang, Z. Manna, and A. Pnueli. Compositional verification of realtime systems. In Proc. 9th IEEE Symp. Logic in Comp. Sei., pages 458-465. IEEE Computer Society Press, 1994.
15. C. Daws, A. Olivero, S. Tripakis, and S. Yovine. The tool Kronos. In Hybrid Systems III, volume 1066 of LNCS, pages 208-219. Springer-Verlag, 1996.
16. C. Daws and S. Yovine. Verification of multirate timed automata with KRONOS: two examples. Technical Report Spectre-95-06, VERIMAG, April 1995.
17. E.A. Emerson. Temporal and modal logic. In J. van Leeuwen, editor, Handbook of Theoretical Computer Science, volume B, pages 995-1072. Elsevier Science Publishers (North-Holland), 1990.
18. T.A. Henzinger and P.-H. Ho. HyTech: The Cornell hybrid technology tool. In Hybrid Systems II, volume 999 of LNCS, pages 265-293. Springer-Verlag, 1995.
19. C. Heitmeyer, R. Jeffords, and B. Labaw. A benchmark for comparing different approaches for specifying and verifying real-time systems. In Proc. Tenth Intl. Workshop on Real- Time Operating Systems and Software, 1993.
20. Т.A. Henzinger and P. Корке. Verification methods for the divergent runs of clock systems. In FTRTFT 94: Formal Techniques in Real-time and Fault-tolerant Systems, volume 863 of LNCS, pages 351-372. Springer-Verlag, 1994.
21. C. Heitmeyer and N. Lynch. The generalized railroad crossing: A case study in formal verification of real-time systems. In Proc. ICCC Real-Time Systems Symposium, pages 120-131. IEEE Press, 1994.
22. T.A. Henzinger, Z. Manna, and A. Pnueli. Temporal proof methodologies for timed transition systems. Inf. and Cотр., 112(2):273-337, August 1994.
23. Y. Kesten, Z. Manna, and A. Pnueli. Verifying clocked transition systems. In Hybrid Systems III, volume 1066 of LNCS, pages 13-40. Springer-Verlag, 1996.
24. L. Lamport. Proving possibility properties. Technical Report 137, Digital Equipment Corporation, Systems Research Center, July 1995.
25. O. Maler, Z. Manna, and A. Pnueli. From timed to hybrid systems. In Proceedings of the REX Workshop "Real-Time: Theory in Practice", volume 600 of LNCS, pages 447-484. Springer-Verlag, 1992.
26. Z. Manna and A. Pnueli. The Temporal Logic of Reactive and Concurrent Systems: Specification. Springer-Verlag, New York, 1991.
27. Z. Manna and A. Pnueli. Temporal verification diagrams. In Proc. Int. Symp. on Theoretical Aspects of Computer Software, volume 789 of LNCS, pages 726-765. Springer-Verlag, 1994.
28. Z. Manna and A. Pnueli. Temporal Verification of Reactive Systems: Safety. Springer-Verlag, New York, 1995.
29. Z. Manna and A. Pnueli. Clocked transition systems. Technical Report STAN-CS-TR-96-1566, Computer Science Department, Stanford University, April 1996.
30. J.S. Ostroff. Temporal Logic of Real-Time Systems. Advanced Software Development Series. Research Studies Press (John Wiley & Sons), Taunton, England, 1990.
31. J.S. Ostroff. A visual toolset for the design of real-time discrete event systems. IEEE Trans, on Control Systems Technology, May 1997. To appear.
32. J.X. Su, D.L. Dill, and C.W. Barrett. Automatic generation of invariants for processor verification. In Formal Methods in Computer-Aided Design, volume 1166 of LNCS, pages 377-388. Springer-Verlag, November 1996.
33. th Intl. Conference on Computer Aided Verification, volume 697 of LNCS, pages 280-291. Springer-Verlag, June 1993.
34. J.U. Skakkebask. A Verification Assistant for a Real-Time Logic. PhD thesis, Technical University of Denmark, 1994.
35. L. Urbina. The generalized railroad crossing: Its symbolic analysis in CLP(R). In Principles and Practice of Constraint Programming, volume 1118 of LNCS, pages 564-567, August 1996.