Efficient constant coefficient multiplication using advanced FPGA architectures

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2147, Issue , 2001, Pages 555-564

  Wirthlin, Michael J ^a   McMurtrey, Brian ^a  

^a BRIGHAM YOUNG UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURE; DISTANCE MEASUREMENT; MOBILE DEVICES; TABLE LOOKUP;

CONSTANT COEFFICIENTS; FPGA ARCHITECTURES; LOOK UP TABLE; MULTIPLIER ARCHITECTURE;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 84949215528     PISSN: 03029743     EISSN: 16113349     Source Type: Journal    
DOI: 10.1007/3-540-44687-7_57     Document Type: Article

References (6)

1. [1] Ken Chapman, “Constant coefficient multipliers for the XC4000E,” Tech. Rep. XAPP 054, Xilinx Corporation, December 11 1996, Version 1.1.
2. [2] Kenneth David Chapman, “Fast integer multipliers fit in FPGA’s,” EDN, p p. 79-80, May 12 1994.
3. Florent de Dinchin and Vincent Lefevre, “Constant multipliers for FPGAs,” in Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, H.R. Arabnia, Ed. June 2000, vol. I, pp. 167-173, CSREA Press.
4. [4] Tim Courtney, Richard Turner, and Roger Woods, “Multiplexer based reconfiguration for Virtex multipliers,” in Field-Programmable Logic and Applications. Proceedings of the 9th International Workshop, FPL 2000, 2000, pp. 749-758.
5. Xilinx Corporation, Virtex-II 1.5V Field-Programmable Gate Arrays, January 2001, DS031-2 (v1.3).
6. B. Hutchings, P. Bellows, J. Hawkins, S. Hemmert, B. Nelson, and M. Rytting, “A cad suite for high-performance fpga design,” in Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, K. L. Pocek and J.M. Arnold, Eds., Napa, CA, April 1999, IEEE Computer Society, pp. 12-24, IEEE.