Implementation of a single chip, pipelined, complex, one-dimensional fast Fourier transform in 0.25 μm bulk CMOS

Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

Volumn 2002-January, Issue , 2002, Pages 335-343

  Currie, S M ^a   Schumacher, P R ^a   Gilbert, B K ^a   Swartzlander, E E ^b   Randall, B A ^c  

^a MAYO CLINIC   (United States)

^b XILINX INC   (United States)

^c UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

Application specific integrated circuits; Clocks; CMOS technology; Computer architecture; Computer interfaces; Design engineering; Distributed computing; Fast Fourier transforms; Pipelines; Random access memory

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CLOCKS; CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; DISTRIBUTED COMPUTER SYSTEMS; INTERFACES (COMPUTER); ONE DIMENSIONAL; PIPELINES; RANDOM ACCESS STORAGE; SIGNAL RECEIVERS; STATIC RANDOM ACCESS STORAGE;

CMOS TECHNOLOGY; COMPUTATION MODULES; COSINE COEFFICIENT; DESIGN ENGINEERING; FFT PROCESSORS; RANDOM ACCESS MEMORY; REDUNDANT COMPUTATION; SPECIAL PURPOSE PROCESSORS;

FAST FOURIER TRANSFORMS;

EID: 84948742537     PISSN: 10636862     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASAP.2002.1030732     Document Type: Conference Paper

References (4)

1. H. L. Groginsky and G. A. Works, "A pipelined Fast Fourier Transform," IEEE Transactions on Computers, Vol. C-19, 1970, pp 1015-1019.
2. E. E. Swartzlander, Jr. and G. Hallnor, "Frequency-Domain Digital Filtering with VLSI," ed. S. Y. Kung, H. J. Whitehouse and T. Kailath, VLSI and Modern Signal Processing, Englewood Cliffs, NJ: Prentice Hall, 1985.
3. E. E. Swartzlander, Jr., VLSI Signal Processing Systems, Boston: Kluwer Academic Publishers, 1986.
4. S. Yu and E.E. Swartzlander, "A pipelined architecture for the multidimensional DFT," IEEE Transactions on Signal Processing, Vol 49, 2001, pp 2096-2102.