What if model checking must be truly symbolic

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 987, Issue , 1995, Pages 1-20

  Hungar, Hardi ^a   Grumberg, Orna ^b   Damma, Werner ^c  

^a OFFIS INSTITUTE FOR INFORMATION TECHNOLOGY   (Germany)

^b TECHNION ISRAEL INSTITUTE OF TECHNOLOGY   (Israel)

^c UNIVERSITY OF OLDENBURG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ARTIFICIAL INTELLIGENCE; COMPUTER SCIENCE; COMPUTERS;

DATA PARTS; SYMBOLIC DESCRIPTION; SYMBOLIC MODEL CHECKING; VERIFICATION PROBLEMS;

MODEL CHECKING;

EID: 84948156200     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-60385-9_1     Document Type: Conference Paper

References (23)

1. Apt, K.R. Ten years of Hoare’s logic: A survey - part I, TOPLAS 3 (1981), 431-483.
2. Apt, K.R. and Olderog, E.-R. Verification of sequential and concurrent programs, Springer, New York (1991).
3. Bradfield, J.C. Verifying temporal properties of systems, Birkhäuser, Boston (1992).
4. Bradfield, J.C. and Stirling, C.P. Verifying temporal properties of processes, CONCUR’90, LNCS 458 (1990), 115-125.
5. Brown, M.C., Clarke, E.M. and Grumberg, O. Characterizing finite Kripke structures in propositional temporal logic, TCS 59 (1988), 115-131.
6. Burch, J.R., Clarke, E.M., McMillan, K.L. and Dill D.L. Sequential circuit verification using symbolic model checking DAC '90, 46-51.
7. Clarke, E.M., Emerson, E.A. and Sistla, A.P. Automatic verification of finite state concurrent systems using temporal logics, POPL '83, 117-126.
8. Clarke, E.M., Grumberg, O. and Long, D.E. Model checking and abstraction, POPL '92, 343-354.
9. Damm, W., Döhmen, G., Helbig, J., Herrmann, R., Josko, B., Kelb, P., Korf, F. and Schlör, R. Correct system level design with VHDL, Tech. Rep., Oldenburg (1994), 54p.
10. Damm, W., Josko, B. and Schlör, R. Specification and verification of VHDL-based system-level hardware designs, in Borger (ed.) Specification and Validation Methods, Oxford Univ. Press, 331-410 (to appear).
11. Dingel, J. and Filkorn, T. Model checking for infinite state systems using data abstraction, assumption-commitment style reasoning and theorem proving, CAV '95, to appear.
12. Emerson, E.A. Temporal and modal logic, in: Handbook of Theor. Comp. Sc., B, North Holland (1990), 997-1072.
13. Floyd, R.W. Assigning meanings to programs, Proc. AMS Symp. Applied Math. 19 (1967), 19-31.
14. Graf, S. Verification of a distributed cache memory by using abstractions, CAV '94, LNCS 818 (1994), 207-219.
15. Grumberg, O. and Long, D.E. Model checking and modular verification, TOPLAS 16 (1994), 843-871.
16. Herrmann, R. and Pargmann, H. Compiling VHDL data types into HDDs, EURO-VHDL '94, 578-583.
17. Hojati, R. and Brayton, R.K. Automatic datapath abstraction in hardware systems, CAV '95, to appear.
18. Josko, B. Verifying the correctness of AADL modules using model checking, in: Stepwise refinement of distributed systems: models, formalisms, correctness, LNCS 430 (1990), 386-400.
19. Manna, Z. Beyong model checking, CAV '94, LNCS 818 (1994), 220-221.
20. Manna, Z. and Pnueli, A. The temporal logics of reactive and concurrent systems. Specification. Springer, New York 1992.
21. Schlör, R. and Damm, W. Specification and verification of system-level hardware designs using timing diagrams, EDAC '93, 518-524.
22. Stirling, C. and Walker, D. Local model checking in the modal mu-calculus, TAPSOFT '89, LNCS 351, 369-383.
23. Wolper, P. Expressing interesting properties of programs in propositional temporal logic, POPL '86, 184-193.