Simplifying circuits for formal verification using parametric representation

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2517, Issue , 2002, Pages 52-69

  Moon, In Ho ^a   Kwak, Hee Hwan ^a   Kukula, James ^a   Shiple, Thomas ^a   Pixley, Carl ^a  

^a SYNOPSYS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; FORMAL VERIFICATION; ITERATIVE METHODS; LOGIC CIRCUITS; MODEL CHECKING; TIMING CIRCUITS;

COMBINATIONAL EQUIVALENCE CHECKING; IMAGE COMPUTATION; INPUT AND OUTPUTS; LOGIC NET; ON THE FLIES; PARAMETRIC REPRESENTATIONS; PROBLEM DOMAIN; SYMBOLIC SIMULATION;

COMPUTER CIRCUITS;

EID: 84948146169     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-36126-x_4     Document Type: Conference Paper

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