CubicWare: A hierarchical design system for deep submicron ASIC

Proceedings - 12th Annual IEEE International ASIC/SOC Conference

Volumn , Issue , 1999, Pages 168-172

  Jang, Myung Soo ^a   Jin, Hoon Sang ^a   Lee, Byoung Hyun ^a   Lee, Jin Yong ^a   Song, Seong Jin ^a   Kim, Taek Soo ^a   Kong, Jeong Taek ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; ELECTRIC POWER UTILIZATION; INTEGRATED CIRCUIT DESIGN; INTEGRATED CIRCUIT LAYOUT;

ACCURATE ESTIMATION; COUPLING CAPACITANCE; DELAY CALCULATION; ESTIMATION ALGORITHM; HIERARCHICAL DESIGN; INTERCONNECT CAPACITANCE; INTERCONNECT PARASITICS; POWER CHARACTERISTIC;

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 84945354992     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASIC.1999.806497     Document Type: Conference Paper

References (14)

1. L. T. Pileggi and R. A. Rohrer, "Asymptotic Waveform Evaulation for Timing Aanlysis", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 9, pp. 3E2-366, 1990.
2. H. S. Jin, M. S. Jang, J. S. Song, J. Y. Lee, T. S. Kim and J. T. Kong, "Dynamic Power Estimation Using the Probabilistic Contribution Measure(PCM)", Proc. IEEE Int. Symposium on Lout Power Design, page in press, 1999.
3. SAMSUNG ELECTRONICS, ASIC Utility Program User's Guide, March 1995.
4. P. K. Hwang, "An O(nlogn) Algorithm for Suboptimal Rectilinear Steiner Trees", IEEE Transactions on Circuits and Systems, vol. 26, n. J, pp. 75-77, January 1979.
5. M. Sarrafssadeh and C. K. Wong, "Hierarchical Steiner Tree Construction in Uniform Orientations", Research report, Dept. of Electrical Engineering and Computer Science, Northwestern University, 1990.
6. M. A. B. JackBon, A. SrinivasanandE. S. Kuh, "Clock Routing for High-Performance ICs", Proceedings of the 27th Design Automation Conference, pp, 573-579, June 1990.
7. SYNOPSYS Inc., Link To Layout Starter Kit, Oct. 1996.
8. Mike Tien-Chien Lee, Vivek Tiwari and et. al, "Power Analysis and Minimization Techniques for Embedded DSP Software", IEEE Trans, on VLSI SYSTEMS, Mar. 1997.
9. F. N. Najm, "Transition Density: A New Measure of Activity in Digital Circuits", IEEE Trans. Gomp. Aided. Design, vol. 12, n. 2, pp. 310-323, February 1993.
10. D. S. Cho, K. H. Lee, G. J. Jang, T. S. Kim and J. T. Kong, "Efficient Modeling Techniques for IR Drop Analysis in ASIC DeBign", Proc. IEEE Int. A SIC/SO C Conf., page in press, 1999.
11. Avant! Inc., Planet Reference Manual, February 1996.
12. Avant! Inc., Apollo Reference Manual, 1998.
13. SYNOPSYS Inc., PowerMill User Manual, 1998.
14. Integrated Measurement System Inc., IMS Manual, 1996.