Characterization of charge trapping in SiO2/HfO2 dielectrics

2003 International Semiconductor Device Research Symposium, ISDRS 2003 - Proceedings

Volumn , Issue , 2003, Pages 322-323

  Degraeve, R ^a   Kerber, A ^b   Cartier, E ^b,c   Pantisano, L ^a   Groeseneken, G ^a,d  

^a IMEC   (Belgium)

^b Infineon assignee at IMEC ^*  (United States)

^c IBM   (United States)

^d UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

CHARGE TRAPPING; CHEMICAL VAPOR DEPOSITION; CMOS INTEGRATED CIRCUITS; DEPOSITION; ELECTRODES; HAFNIUM OXIDES; IODINE; POLYCRYSTALLINE MATERIALS; SEMICONDUCTOR DEVICES; THRESHOLD VOLTAGE; TRANSISTORS; VAPOR DEPOSITION; WATER;

ATOMIC LAYER CHEMICAL VAPOR DEPOSITION; DOPANT ACTIVATION; FORMING GAS ANNEALING; INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS; POLY-SI ELECTRODE; TRANSISTOR CHARACTERISTICS; TRANSISTOR PARAMETERS; TRAPPING EFFECTS;

GATE DIELECTRICS;

EID: 84945315896     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISDRS.2003.1272115     Document Type: Conference Paper

References (5)

1. International Technology Roadmap for Semiconductors (SIA, San Jose, CA) http://public.itrs.net. 2001.
2. A. Kerber et al., Elec. Dev. Lett., vol. 24, no. 2, pp. 87-89, 2003.
3. L. Paritisano et al., VLSI Techn. Symp., pp. 163-164, 2003.
4. A. Kerber et al., presented at INFOS 2003.
5. E. Cartier ct al, presented at INFOS 2003.