Low-power hybrid STT/CMOS system-on-chip embedding non-volatile magnetic memory blocks

Conference Proceedings - 13th IEEE International NEW Circuits and Systems Conference, NEWCAS 2015

Volumn , Issue , 2015, Pages

  Layer, Christophe ^a   Jabeur, Kotb ^a   Gros, Stephane ^a   Becker, Laurent ^a   Paoli, Pierre ^a   Bernard Granger, Fabrice ^a   Javerliac, Virgile ^a   Dieny, Bernard ^a  

^a UNIV GRENOBLE ALPES   (France)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BENCHMARKING; COMPUTER SOFTWARE PORTABILITY; DATA COMPRESSION; DIGITAL STORAGE; ENERGY EFFICIENCY; MAGNETIC STORAGE; MEMORY ARCHITECTURE; MICROPROCESSOR CHIPS; MOBILE DEVICES; PROGRAMMABLE LOGIC CONTROLLERS;

COMPLEX COMPUTING SYSTEMS; COMPRESSION ALGORITHMS; ENERGY EFFICIENT COMPUTING; HETEROGENEOUS TECHNOLOGY; LOW POWER TECHNOLOGIES; PERFORMANCE ESTIMATION; PROCESSING PERFORMANCE; SINGLE BIT MEMORY CELL;

SYSTEM-ON-CHIP;

EID: 84945157235     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NEWCAS.2015.7181999     Document Type: Conference Paper

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