Code tiling for improving the cache performance of PDE solvers

Proceedings of the International Conference on Parallel Processing

Volumn 2003-January, Issue , 2003, Pages 615-624

  Huang, Qingguang ^a   Xue, Jingling ^a   Vera, X ^b  

^a UNIVERSITY OF NEW SOUTH WALES   (Australia)

^b Institutionen för Datateknik Mälardalens Högskola   (Sweden)

Author keywords

Australia; Computer science; Data engineering; Jacobian matrices; Multidimensional systems; Partial differential equations; Processor scheduling; Tiles

Indexed keywords

BUFFER STORAGE; CACHE MEMORY; COMPUTER SCIENCE; JACOBIAN MATRICES; MEMORY ARCHITECTURE; METADATA; PARTIAL DIFFERENTIAL EQUATIONS; TILE;

AUSTRALIA; COMPILER TECHNIQUES; DATA ENGINEERING; MACHINE ARCHITECTURES; MULTIDIMENSIONAL SYSTEMS; OBJECTIVE FUNCTIONS; PERFORMANCE CURVE; PROCESSOR SCHEDULING;

CODES (SYMBOLS);

EID: 84944744196     PISSN: 01903918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICPP.2003.1240630     Document Type: Conference Paper

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