Scheduling algorithms with bus bandwidth considerations for SMPs

Proceedings of the International Conference on Parallel Processing

Volumn 2003-January, Issue , 2003, Pages 547-554

  Antonopoulos, C D ^a   Nikolopoulos, D S ^b   Papatheodorou, T S ^a  

^a UNIVERSITY OF PATRAS   (Greece)

^b William and Mary   (United States)

Author keywords

Bandwidth; Educational institutions; High performance computing; Information systems; Interference; Processor scheduling; Scheduling algorithm; Switched mode power supply; Systems engineering and theory; Yarn

Indexed keywords

ALGORITHMS; BANDWIDTH; BUSES; COMPUTATION THEORY; COMPUTER OPERATING SYSTEMS; INFORMATION SYSTEMS; MULTITASKING; PARALLEL PROCESSING SYSTEMS; SCHEDULING; SHAPE MEMORY EFFECT; SWITCHED MODE POWER SUPPLIES; WAVE INTERFERENCE; YARN;

BANDWIDTH REQUIREMENT; EDUCATIONAL INSTITUTIONS; HIGH PERFORMANCE COMPUTING; MEMORY HIERARCHY OPTIMIZATIONS; PERFORMANCE MONITORING; PROCESSOR SCHEDULING; SCHEDULING POLICIES; SYSTEMS ENGINEERING AND THEORIES;

SCHEDULING ALGORITHMS;

EID: 84944730283     PISSN: 01903918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICPP.2003.1240622     Document Type: Conference Paper

References (17)

1. G. Alverson, S. Kahan, R. Corry, C. McCann, and B. Smith. Scheduling on the Tera MTA. In Proc. of the first Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP'95), LNCS Vol. 949, pages 19-44, Santa Barbara, CA, Apr. 1995.
2. N. M. Amato, J. Perdue, A. Pietracaprina, G. Pucci, and M. Mathis. Predicting Performance on SMPs. A Case Study: The SGI Power Challenge. In Proc. of the International Parallel and Distributed Processing Symposium (IPDPS 2000), Cancun, Mexico, May 2000.
3. C. D. Antonopoulos, D. S. Nikolopoulos, and T. S. Papatheodorou. Scheduling Algorithms with Bus Bandwidth Considerations for SMPs. Technical Report HPCLAB-TR-090703, High Performance Information Systems Lab, University of Patras, July 2003.
4. Meeting the I/O Bandwidth Challenge: How HyperTransport Technology Accelerates Performance in Key Applications. Technical report, HyperTransport Consortium, http://www.hypertransport.org/, December 2002.
5. Infiniband Architecture Specification, Release 1.1. Technical report, Infiniband Trade Association, http://www.infinibandta.org, November 2002.
6. H. Jin, M. Frumkin, and J. Yan. The OpenMP Implementation of NAS Parallel Benchmarks and its Performance. Technical Report NAS-99-011, NASA Ames Research Center, 1999.
7. J. D. McCalpin. Memory Bandwidth and Machine Balance in Current High Performance Computers. Technical Committee on Computer Architecture (TCCA) Newsletter, December 1995.
8. C. McCann, R. Vaswani, and J. Zahorjan. A Dynamic Processor Allocation Policy for Multiprogrammed Shared Memory Multiprocessors. ACM Transactions on Computer Systems, 11(2):146-178, May 1993.
9. A. Snavely and D. Tullsen. Symbiotic Job Scheduling for a Simultaneous Multithreading Processor. In Proc. of the 9th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS'IX), pages 234-244, Cambridge, Massachusetts, Nov. 2000.
10. M. Squillante and E. Lazowska. Using Processor-Cache Affinity Information in Shared-Memory Multiprocessor Scheduling. IEEE Transactions on Parallel and Distributed Systems, 4(2):131-143, Feb. 1993.
11. G. Suh, S. Devadas, and L. Rudloph. Analytical Cache Models with Applications to Cache Partitioning. In Proc. of the 15th ACM International Conference on Supercomputing (ICS'01), pages 1-12, Sorrento, Italy, June 2001.
12. G. Suh, L. Rudolph, and S. Devadas. Effects of Memory Performance on Parallel Job Scheduling. In Proc. of the 8th Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP'02), pages 116-132, Edinburgh, Scotland, June 2002.
13. J. Torrellas, A. Tucker, and A. Gupta. Evaluating the Performance of Cache-Affinity Scheduling in Shared-Memory Multiprocessors. Journal of Parallel and Distributed Computing, 24(2):139-151, Feb. 1995.
14. A. Tucker and A. Gupta. Process Control and Scheduling Issues for Multiprogrammed Shared-Memory Multiprocessors. In Proc. of the 12th ACM Symposium on Operating Systems Principles (SOSP'89), pages 159-166, Litchfield Park, Arizona, Dec. 1989.
15. R. Vaswani and J. Zahorjan. The Implications of Cache Affinity on Processor Scheduling for Multiprogrammed Shared Memory Multiprocessors. In Proc. of the 13th ACM Symposium on Operating System Principles (SOSP'91), pages 26-40, Pacific Grove, California, Oct. 1991.
16. S. C. Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Gupta. The splash-2 programs: Characterization and methodological considerations. In Proceedings of the 22nd Annual International Symposium on Computer Architecture (ISCA'95), pages 24-36, June 1995.
17. M. Zagha, B. Larson, S. Turner, and M. Itzkowitz. Performance Analysis Using the MIPS R10000 Performance Counters. In Proceedings of the SuperComputing 1996 Conference (SC96), Pittsburgh, USA, November 1996.