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Volumn 2335, Issue , 2002, Pages 145-164

A framework for translating models and specifications

Author keywords

[No Author keywords available]

Indexed keywords

PROGRAM COMPILERS;

EID: 84944221185     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-47884-1_9     Document Type: Conference Paper
Times cited : (15)

References (31)
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    • Apt, K.R.1    Francez, N.2    Katz, S.3
  • 3
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    • Technical Report CS-2002-05, Computer Science Department, The Technion
    • M. Berg and S. Katz. Property transformations for translations. Technical Report CS-2002-05, Computer Science Department, The Technion, 2002.
    • (2002) Property Transformations for Translations
    • Berg, M.1    Katz, S.2
  • 10
    • 84948168602 scopus 로고    scopus 로고
    • DSPIN: A dynamic extension of SPIN
    • C. Demartini, R. Iosif, and R. Sisto. dSPIN: A dynamic extension of SPIN. In SPIN, pages 261–276, 1999.
    • (1999) SPIN , pp. 261-276
    • Demartini, C.1    Iosif, R.2    Sisto, R.3
  • 13
    • 0023365727 scopus 로고
    • Statecharts: A visual formalism for complex systems
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    • (1987) Science of Computer Programming , vol.8 , pp. 231-274
    • Harel, D.1
  • 15
    • 84944196475 scopus 로고    scopus 로고
    • Using the bandera tool set to model-check properties of concurrent java software
    • June 2001. Invited tutorial paper
    • J. Hatcliff and M. Dwyer. Using the bandera tool set to model-check properties of concurrent java software. In International Conference on Concurrency Theory (CONCUR), June 2001. Invited tutorial paper.
    • International Conference on Concurrency Theory (CONCUR)
    • Hatcliff, J.1    Dwyer, M.2
  • 21
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    • Refinement with global equivalence proofs in temporal logic
    • D. Peled, V. Pratt, and G. Holzmann, editors, American Mathematical Society, DIMACS Series in Discrete Mathematics and Theoretical Computer Science, vol
    • S. Katz. Refinement with global equivalence proofs in temporal logic. In D. Peled, V. Pratt, and G. Holzmann, editors, Partial Order Methods in Verification, pages 59–78. American Mathematical Society, 1997. DIMACS Series in Discrete Mathematics and Theoretical Computer Science, vol. 29.
    • (1997) Partial Order Methods in Verification , pp. 59-78
    • Katz, S.1
  • 23
    • 0025506042 scopus 로고
    • Interleaving set temporal logic. Theoretical Computer Science, 75:263–287, 1990. Preliminary version appeared in the 6th ACM-PODC
    • S. Katz and D. Peled. Interleaving set temporal logic. Theoretical Computer Science, 75:263–287, 1990. Preliminary version appeared in the 6th ACM-PODC, 1987.
    • (1987)
    • Katz, S.1    Peled, D.2
  • 25
    • 84944225992 scopus 로고
    • Computer-aided Verification of Coordinating Processes. Princeton University Press
    • R.P. Kurshan. Computer-aided Verification of Coordinating Processes. Princeton University Press, 1994.
    • (1994)
    • Kurshan, R.P.1
  • 26
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    • The Temporal Logic of Reactive and Concurrent Systems: Specification. Springer-Verlag
    • Z. Manna and A. Pnueli. The Temporal Logic of Reactive and Concurrent Systems: Specification. Springer-Verlag, 1992.
    • (1992)
    • Manna, Z.1    Pnueli, A.2
  • 27
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    • Symbolic Model Checking: An Approach to the State Explosion Problem. Kluwer Academic Publishers
    • K. L. McMillan. Symbolic Model Checking: An Approach to the State Explosion Problem. Kluwer Academic Publishers, 1993.
    • (1993)
    • McMillan, K.L.1
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    • http://wwwbrauer.informatik.tu-muenchen.de/gruppen/theorie/KIT/.
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    • Formal verification for fault-tolerant architectures: Prolegomena to the design of PVS
    • Sam Owre, John Rushby, Natarajan Shankar, and Friedrich von Henke. Formal verification for fault-tolerant architectures: Prolegomena to the design of PVS. IEEE Transactions on Software Engineering, 21(2):107–125, February 1995.
    • (1995) IEEE Transactions on Software Engineering , vol.21 , Issue.2 , pp. 107-125
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.