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Volumn 1940, Issue , 2000, Pages 73-87

Loop termination prediction

Author keywords

[No Author keywords available]

Indexed keywords

ITERATIVE METHODS;

EID: 84944074448     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-39999-2_8     Document Type: Conference Paper
Times cited : (11)

References (16)
  • 5
    • 84944121225 scopus 로고
    • IBM. The PowerPC Architecture: A Specification for a New Family of RISC Processors. Morgan Kaufmann Publishers
    • IBM. The PowerPC Architecture: A Specification for a New Family of RISC Processors. Morgan Kaufmann Publishers, 1994.
    • (1994)
  • 6
    • 84944121226 scopus 로고    scopus 로고
    • Intel. IA-64 Application Developer’s Architecture Guide. Intel Corporation, Order Number 245188-001
    • Intel. IA-64 Application Developer’s Architecture Guide. Intel Corporation, Order Number 245188-001, 1999.
    • (1999)
  • 8
    • 0003506711 scopus 로고
    • Technical Report TN-36, Digital Equipment Corporation, Western Research Lab
    • S. McFarling. Combining branch predictors. Technical Report TN-36, Digital Equipment Corporation, Western Research Lab, June 1993.
    • (1993) Combining Branch Predictors
    • McFarling, S.1
  • 9
    • 0027578544 scopus 로고
    • Branch target buffer design and optimization
    • C. H. Perleberg and A. J. Smith. Branch target buffer design and optimization. IEEE Transactions on Computers, 42(4):396–412, 1993.
    • (1993) IEEE Transactions on Computers , vol.42 , Issue.4 , pp. 396-412
    • Perleberg, C.H.1    Smith, A.J.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.