An overview of stress free polishing of Cu with ultra low-k(k<2.0) films

Proceedings of the IEEE 2003 International Interconnect Technology Conference, IITC 2003

Volumn , Issue , 2003, Pages 83-85

  Pallinti, J ^a   Lakshminarayanan, S ^a   Barth, W ^a   Wright, P ^a   Lu, M ^a   Reder, S ^a   Kwak, L ^a   Catabay, W ^a   Wang, D ^b   Ho, F ^b  

^a AGERE SYSTEMS   (United States)

^b ACM Research Corp   (United States)

Author keywords

Chemical technology; Copper; Delamination; Etching; Large scale integration; Logic; Planarization; Rough surfaces; Stress; Surface roughness

Indexed keywords

DELAMINATION; ETCHING; LSI CIRCUITS; POLISHING; STRESSES; SURFACE ROUGHNESS;

CHEMICAL TECHNOLOGIES; COPPER REMOVAL; LOGIC; PLANARIZATION; POLISHING TECHNOLOGY; PROCESS PERFORMANCE; ROUGH SURFACES; ULTRA LOW-K;

COPPER;

EID: 84944040537     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.2003.1219719     Document Type: Conference Paper

References (4)

1. David Wang et al., "Stress Free Polishing advances copper integration with ultra low-k dielectrics", Solid State Technology, Oct 2001, pp. 101-106
2. Source: 2001 CMP-MIC Conference - 600P/00/0349 by CMC and ISMT
3. "Interconnect Section", ITRS Roadmap, 2001 Edition, pp. 18-19
4. G. B. Alers et al., "Trade-off between reliability and post-CMP defects during recrystallization anneal for copper damascene interconnects", International reliability physics symposium proceedings 2001, pp. 350-354.