Test consideration for nanometer scale CMOS circuits

Proceedings of the IEEE VLSI Test Symposium

Volumn 2003-January, Issue , 2003, Pages 313-315

  Roy, K ^a   Mak, T M ^b   Cheng, Kwang Ting ^c  

^a PURDUE UNIVERSITY   (United States)

^b INTEL CORPORATION   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Circuit testing; CMOS technology; Energy consumption; Energy management; Frequency; Integrated circuit testing; Leakage current; Temperature sensors; Threshold voltage; Tunneling

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRON TUNNELING; ENERGY MANAGEMENT; ENERGY UTILIZATION; INTEGRATED CIRCUITS; LEAKAGE CURRENTS; POWER MANAGEMENT; TEMPERATURE SENSORS; THRESHOLD VOLTAGE; VLSI CIRCUITS;

CIRCUIT TESTING; CMOS TECHNOLOGY; EXPONENTIAL INCREASE; FREQUENCY; INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS; NANOMETER-SCALE CMOS; POWER MANAGEMENT STRATEGIES; POWER MANAGEMENT TECHNIQUES;

INTEGRATED CIRCUIT TESTING;

EID: 84943545414     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTEST.2003.1197668     Document Type: Conference Paper

References (8)

1. K. Roy, S. Mukhopadhaya, and H. Mahmoodi-Meimand, "Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicron CMOS Circuits," IEEE Proceedings, pp. 305-327, Feb. 2003.
2. K-T Cheng, S. Dey, M. Rodgers, and K. Roy, "Test Challenges for Deep Sub-Micron Technologies," ACM/IEEE DAC, 2000.
3. Wei. et. al.., "Design and Optimization of Dual Threshold Circuits for Low-Voltage Low-Power Applications,"IEEE Trans. on VLSI Systems, Mar. 1999.
4. J.-J. Liou et. al., "Performance Sensitivity Analysis Using Statistical Methods and Its Applications to Delay Testing." ASP DAC, Jan. 2000.
5. J.-J. Liou, et al., "False-Path- Aware Statistical Timing Analysis and Efficient Path Selection for Delay Testing and Timing Validation. ACM/IEEE Design Auto. Conf., June 2002.
6. A. Krstic, et al., "Delay Defect Diagnosis Based Upon Statistical Timing Models - The First Step", DATE, March 2003.
7. A. Keshavarzi, et. al., "Multi-parameter CMOS IC Testing with Increased Sensitivity for IDDQ," Intl. Test Conf., 2000.
8. S. Bhunia, K. Roy, and J. Segura, "A Novel Wavelet Transform Based Transient Current Analysis for Fault Detection and Analysis," ACM/IEEE DAC, 2002.