Systolic interpolation architectures for soft-decoding Reed-Solomon codes

IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation

Volumn 2003-January, Issue , 2003, Pages 81-86

  Ahmed, A ^a   Shanbhag, N R ^a   Koetter, R ^a  

^a United States of America   (United States)

Author keywords

Computer architecture; Delay; Hardware; Interpolation; Iterative decoding; Kernel; Pipeline processing; Polynomials; Reed Solomon codes; Throughput

Indexed keywords

ALGORITHMS; BLOCK CODES; CODES (SYMBOLS); COMPUTER HARDWARE; HARDWARE; INTERPOLATION; ITERATIVE DECODING; ITERATIVE METHODS; PIPELINE CODES; PIPELINE PROCESSING SYSTEMS; POLYNOMIALS; REED-SOLOMON CODES; SIGNAL PROCESSING; THROUGHPUT;

ALGEBRAIC SOFT DECODING; DELAY; HIGH THROUGHPUT IMPLEMENTATION; INTERPOLATION ALGORITHMS; KERNEL; PIPELINE PROCESSING; POLYNOMIAL COEFFICIENTS; PROPOSED ARCHITECTURES;

COMPUTER ARCHITECTURE;

EID: 84943247547     PISSN: 15206130     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SIPS.2003.1235648     Document Type: Conference Paper

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