Silicon nano-transistors and breaking the 10 nm physical gate length barrier

Device Research Conference - Conference Digest, DRC

Volumn 2003-January, Issue , 2003, Pages 123-126

  Chau, R ^a   Doyle, B ^a   Doczy, M ^a   Datta, S ^a   Hareland, S ^a   Jin, B ^a   Kavalieros, J ^a   Metz, M ^a  

^a INTEL CORPORATION   (United States)

Author keywords

CMOS technology; Delay; Laboratories; Lifting equipment; Logic devices; Manufacturing; Microprocessors; Production; Silicon; Transistors

Indexed keywords

LABORATORIES; LOGIC DEVICES; MANUFACTURE; MICROPROCESSOR CHIPS; PRODUCTION; SILICON; TRANSISTORS;

CMOS TECHNOLOGY; DELAY; ENERGY DELAY; GATE LENGTH; LIFTING EQUIPMENTS;

CMOS INTEGRATED CIRCUITS;

EID: 84942601668     PISSN: 15483770     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DRC.2003.1226901     Document Type: Conference Paper

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