A power-line noise coupling estimation methodology for architectural exploration of mixed-signal systems

2003 Southwest Symposium on Mixed-Signal Design, SSMSD 2003

Volumn , Issue , 2003, Pages 133-137

  Lundgren, J ^a   Ytterdal, T ^b   Eriksson, P ^c   Oelmann, B ^a   Abdalla, M ^a   O'Nils, M ^a  

^a MID SWEDEN UNIVERSITY   (Sweden)

^b NORWEGIAN UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Norway)

^c ACREO AB   (Sweden)

Author keywords

Circuit noise; Circuit simulation; Coupling circuits; Electronic mail; Interference; Noise level; Power system modeling; Power systems; SPICE; System on a chip

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CIRCUIT SIMULATION; COMPUTER SIMULATION LANGUAGES; COUPLED CIRCUITS; ELECTRIC NETWORK ANALYSIS; ELECTRIC SIGNAL SYSTEMS; ELECTRONIC MAIL; INTEGRATED CIRCUIT INTERCONNECTS; LOGIC DESIGN; SIGNAL SYSTEMS; SPICE; STANDBY POWER SYSTEMS; SYSTEM-ON-CHIP; WAVE INTERFERENCE;

CIRCUIT NOISE; ESTIMATION METHODOLOGIES; MIXED-SIGNAL SYSTEMS; NOISE LEVELS; POWER DISTRIBUTION NETWORK; POWER SYSTEM MODEL; SYSTEM DESIGN LANGUAGES; SYSTEM ON A CHIP;

MIXED SIGNAL INTEGRATED CIRCUITS;

EID: 84942518357     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SSMSD.2003.1190412     Document Type: Conference Paper

References (12)

1. Verghese N.K., Schmerbeck T.J., Allstot D.J., Simulation techniques and solutions for mixed-signal coupling in integrated circuits, Kluwer Academic Publishers, ISBN 0-7923-9544-1, 1995.
2. TMA MEDICI: Two Dimensional Device Simulation Program, Version 1, Volume 1, Technology Modelling Associates, Inc., 1992.
3. Nagel L., SPICE2: A computer program to simulate semiconductor circuits, Electronics Research Lab., Univ. Calif. Berkeley, Memo UCB/ERL M520, May 1975.
4. Gielen G.G.E., Rutenbar R.A., "Computer-Aided Design of Analog and Mixed-Signal Integrated Circuits", Proceedings of the IEEE, vol.88, no.12, December 2000.
5. Ismail Y.I., Friedman E.G., Neves J.L., "Performance Criteria for Evaluating the Importance of On-Chip Inductance", Proceedings of the IEEE, ISCAS, Vol. 2, pp. 224-247, 1998.
6. Ismail Y.I., Friedman E.G., Neves J.L., "Figures of Merit to Characterize the Impedance of On-Chip Inductance", IEEE Transitions on VLSI Systems, Vol. 7, No. 4, pp. 442-449, December 1999.
7. SystemC, www.systemc.org
8. Lundgren J., Oelmann B., Ytterdal T., Eriksson P., Abdalla M., O'Nils M., "Behavioral Simulation of Power Line Noise Coupling in Mixed-Signal Systems using SystemC", Proceedings of the IEEE annual Symposium on VLSI, February 2003.
9. Campbell M., Heijne E.H.M., Meddeler G., Pernigotti E., Snoeys W., "Readout chip for a 64 x 64 pixel matrix with 15-bit single photon counting", IEEE Transactions on Nuclear Science, Volume 45, Issue 3 Part 1, June 1998, Pages 751-753.
10. Brönnimann Ch., et al., "A pixel read-out chip for the PILATUS project", Nuclear Instrumentation and Methods - A, vol. 465, no. 1, pp. 235-239, June 2001.
11. Oelmann B., Abdalla M., O'Nils M., "All-digital window discriminator for photon counting pixel detectors", IEE Electronics Letters, Vol. 37, No. 6, March 2001, pp. 373-374.
12. O'Nils M., Abdalla M., Oelmann M., "Low Digital Interference Counter for Photon Counting Pixel Detectors", Nuclear Instruments and Methods - A, Vol.487, No.3 pp. 323-330, Aug. 2002.