A high-performance/low-power on-chip memory-path architecture with variable cache-line size

IEICE Transactions on Electronics

Volumn E83-C, Issue 11, 2000, Pages 1716-1722

  Inoue, Koji ^a   Kai, Koji ^b   Murakami, Kazuaki ^a  

^a KYUSHU UNIVERSITY   (Japan)

^b Institute of Systems & Information Technologies/KYUSHU   (Japan)

Author keywords

Cache; High bandwidth; Low power; Merged DRAM logic LSIs; Variable line size

Indexed keywords

EID: 33746341818     PISSN: 09168524     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (13)

1. M.D. Hill, J.R. Larus, A.R. Lebeck, M. Talluri, and D.A. Wood, "WARTS: Wisconsin architectural research tool set," http://www.cs.wisc.edu/larus/warts.html, University of Wisconsin, Madison.
2. K. Inoue, K. Koji, and K. Murakami, "High band-width, variable line-size cache architecture for merged DRAM/logic LSIs," IEICE Trans. Electron., vol.E81-C, no.9, pp.1438-1447, Sept. 1998.
3. K. Inoue, K. Koji, and K. Murakami, "Dynamically variable line-size cache architecture for merged DRAM/logic LSIs," IEICE Trans. Inf. & Syst., vol.E83-D, no.5, pp.1048-1057, May 2000.
4. T.L. Johnson, M.C. Merten, and W.W. Hwu, "Run-time spatial locality detection and optimization," Proc. 30th Annual International Symposium on Microarchitecture, pp.57-64, Dec. 1997.
5. S. Kumar and C. Wilkerson, "Exploiting spatial locality in data caches using spatial footprints," Proc. 25th Annual International Symposium on Computer Architecture, pp.357-368, June 1998.
6. K. Murakami, S. Shirakawa, and H. Miyajima, "Parallel processing RAM chip with 256 Mb DRAM and quad processors," 1997 ISSCC Digest of Technical Papers, pp.228-229, Feb. 1997.
7. T. Ohsawa, K. Kai, and K. Murakami, "Optimizing the DRAM refresh count for merged DRAM/logic LSIs," Proc. 1998 International Symposium on Low Power Electronics and Design, pp.82-87, Aug. 1998.
8. D. Patterson, T. Anderson, N. Cardwell, R. Fromm, K. Keeton, C. Kozyrakis, R. Thomas, and K. Yelick, "Intelligent RAM (IRAM): Chips that remember and compute," 1997 ISSCC Digest of Technical Papers, pp.224-225, Feb. 1997.
9. A. Saulsbury, F. Pong, and A. Nowatzyk, "Missing the memory wall: The case for processor/memory integration," Proc. 23rd Annual International Symposium on Computer Architecture, pp.90-101, May 1996.
10. SPEC (Standard Performance Evaluation Corporation), URL: http://www.specbench.org/osg/cpu92, http://www.specbench.org/osg/cpu95.
11. K.M. Wilson and K. Olukotun, "Designing high bandwidth on-chip caches," Proc. 24th Annual International Symposium on Computer Architecture, pp.121-132, June 1997.
12. P.V. Vleet, E. Anderson, L. Brown, J.L. Baer, and A. Karlin, "Pursuing the performance potential of dynamic cache line sizes," Proc. 1999 IEEE International Conference on Computer Design: VLSI in Computer & Processors, pp.528-537, Oct. 1999.
13. S.J.E. Wilton and N.P. Jouppi, "CACTI: An enhanced cache access and cycle time model," IEEE J. Solid-State Circuits, vol.31, no.5, pp.677-688, May 1996.