Reduction of bus transitions with partial bus-invert coding

Electronics Letters

Volumn 34, Issue 7, 1998, Pages 642-643

  Shin, Youngsoo ^a   Chae, Soo Ik ^a   Choi, Kiyoung ^a  

^a Seoul National University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE;

PARTIAL BUS INVERT (PBI) CODING;

ENCODING (SYMBOLS);

EID: 0032473653     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19980424     Document Type: Article

References (6)

1. LIU, D., and SVENSSON, C.: 'Power consumption estimation in CMOS VLSI chips', IEEE J. Solid State Circuits, 1994, 29, (6), pp. 663-670
2. STAN, M.R., and BURLESON, W.P : 'Bus-invert coding for low-power I/O'. IEEE Trans. VLSI Syst., 1995, 3, (1), pp. 49-58
3. SU, C.L., TSUI, C.Y., and DESPAIN, A.M.: 'Saving power in the control path of embedded processors', IEEE Des. Test Comput., 1994, 11, (4), pp. 24-30
4. BEMNI, L , DE MICHELI, G., MACII, E., SCIUTO, D., and SILVANO, C.: 'Asymptotic zero-transition activity encoding for address busses in low-power microprocessor-based systems'. Proc. Great Lakes Symp. on VLSI, 1997, pp. 77-82
5. BENINI, L., DE MICHELI, G., MACII, E., PONCINO, M., and QUER, S.: 'System-level power optimization of special purpose applications: The Beach solution'. Proc. Int. Symp. on Low Power Electronics and Design, 1997, pp. 24-29
6. PANDA, P.R, and DUTT, N D: '1995 high level synthesis design L. repository'. Proc. Int. Symp. on System Synthesis. 1995