Junction Optimization for Embedded 40nm FN/FN Flash Memory

2015 IEEE 7th International Memory Workshop, IMW 2015

Volumn , Issue , 2015, Pages

  Baiano, Alessandro ^a   Van Duuren, Michiel ^a   Van Der Vegt, Erik ^a   Schippers, Bob ^a   Beurze, Robert ^a   Mofrad, Daniel Tajari ^a   Van Zwol, Hans ^a   Chen, Yu ^a   Chiang, Jed ^a   Lokker, Han ^a   Van Dijk, Kitty ^a   Verbree, Jouke ^a   Chen, Yi Ning ^a   Garbe, Jochen ^a   Verhaar, Rob ^a   Dormans, Do ^a  

^a NXP SEMICONDUCTORS   (Netherlands)

Author keywords

40nm 2T cell; drain disturb; embedded non volatile memory; TCAD simulation

Indexed keywords

CELL MEMBRANES; CYTOLOGY; NONVOLATILE STORAGE; T-CELLS;

2T CELL; ARRAY ARCHITECTURE; CELL TECHNOLOGY; CHANNEL LENGTH; DRAIN DISTURB; NON-VOLATILE MEMORY; TCAD SIMULATION;

FLASH MEMORY;

EID: 84939522083     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IMW.2015.7150292     Document Type: Conference Paper

References (7)

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6. G. Tao et al., proc. ICMTD 2007, Giens, p. 113 (2007)
7. D.R. Nair et al. "Drain Disturb During CHISEL Programming of NOR Flash EEPROMs-Physical Mechanisms and Impact of Technological Parameters," IEEE Trans. On Electron Devices, vol. 51, No. 5, May 2004.