Swap-And-Randomize: A Method for Building Low-Latency HPC Interconnects

IEEE Transactions on Parallel and Distributed Systems

Volumn 26, Issue 7, 2015, Pages 2051-2060

  Fujiwara, Ikki ^a   Koibuchi, Michihiro ^b   Matsutani, Hiroki ^c   Casanova, Henri ^d  

^a NATIONAL INSTITUTE OF INFORMATICS   (Japan)

^b GRADUATE UNIVERSITY FOR ADVANCED STUDIES   (Japan)

^c KEIO UNIVERSITY   (Japan)

^d UNIVERSITY OF HAWAII   (United States)

Author keywords

cabinet layout; high performance computing; interconnection networks; Network topologies

Indexed keywords

CABLES; COMPLEX NETWORKS; ELECTRIC NETWORK TOPOLOGY; INTERCONNECTION NETWORKS (CIRCUIT SWITCHING);

CABINET LAYOUT; EXISTING SYSTEMS; HIGH PERFORMANCE COMPUTING; LARGE-SCALE COMPUTING SYSTEMS; NETWORK SIMULATION; NETWORK TOPOLOGY; RANDOM NETWORK; RANDOM TOPOLOGY;

TOPOLOGY;

EID: 84933575563     PISSN: 10459219     EISSN: None     Source Type: Journal    
DOI: 10.1109/TPDS.2014.2340863     Document Type: Article

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