Effects of thin SiN interface layer on transient I-V characteristics and stress induced degradation of high-k dielectrics

IEEE International Reliability Physics Symposium Proceedings

Volumn 2004-January, Issue January, 2004, Pages 587-588

  Kang, C Y ^a   Cho, H J ^a   Kang, C S ^a   Choi, R ^a   Kim, Y H ^a   Rhee, S J ^a   Choi, C H ^a   Akbar, S M ^a   Lee, J C ^a  

^a The University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHARGE TRAPPING; THRESHOLD VOLTAGE;

BULK CHARGE TRAPPING; HIGH-K DIELECTRIC; INTERFACE STRUCTURES; INTERFACIAL LAYER; IV CHARACTERISTICS; MOBILITY DEGRADATION; STRESS-INDUCED DEGRADATION; TIME DEPENDENT THRESHOLDS;

SILICON NITRIDE;

EID: 84932125625     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RELPHY.2004.1315402     Document Type: Conference Paper

References (4)

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2. D. Schroder, et al., J. Appl. Phys., vol. 94, p. 21 (2003)
3. K. Onishi, et al. Tech. Dig. IEDM, p 659 (2001)
4. L, Pantisano, et al., Symp. VLSI Tech. Dig., p. 163 (2003)