Techniques for Small-Signal Analysis of Semiconductor Devices

IEEE Transactions on Electron Devices

Volumn 32, Issue 10, 1985, Pages 2028-2037

  Laux, Steven E ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 84925794148     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/T-ED.1985.22235     Document Type: Article

References (26)

1. W. L. Engl, H. K. Dirks, and B. Meinerzhagen, “Device modeling,” Proc. IEEE, vol. 71, no. 1, pp. 10–33, Jan. 1983.
2. S. Selberherr, Analysis and Simulation of Semiconductor Devices. New York: Springer-Verlag, 1984.
3. B. V. Gokhale, “Numerical solutions for a one-dimensional silicon n-p-n-transistor,” IEEE Trans. Electron Devices, vol. ED-17, pp. 594–602, 602, Aug. 1970.
4. M. Kurata, “A small-signal calculation for one-dimensional transistors,” IEEE Trans. Electron Devices, vol. ED-18, pp, 200–210, Mar. 1971.
5. V. Temple and J. Shewchun, “Exact frequency dependent complex admittance of the MOS diode including surface states, Shockley- Read-Hall Read-Hall (SRH) impurity effects, and low temperature dopant impurity response,” Solid-State Electron., vol. 16, no. 1, pp. 93–113, Jan. 1973.
6. C. F. Smiley, L. D. Yau, and C. T. Sah, “Application of the transmission line equivalent circuit model to the analysis of the PN junction admittance under d.c. bias,” Solid-State Electron., vol. 16, no. 8, pp. 895–901, Aug. 1973.
7. M. A. Green and J. Shewchun, “Application of the small-signal trans-mission line equivalent circuit model to the a.c., d.c. and transient analysis of semiconductor devices,” Solid-State Electron., vol. 17, no. 9, pp. 941–949, Sept. 1974.
8. M. Reiser, “A two-dimensional numerical FET model for DC, AC, and large-signal analysis,” IEEE Trans. Electron Devices, vol. ED-20, 20, pp. 35–45, Jan. 1973.
9. D. E. Ward and R. W. Dutton, “A charge-oriented model for MOS transistor capacitances,” IEEEJ. Solid-State Circuits, vol. SC-13, pp. 703–707, Oct. 1978.
10. J. A. Robinson, Y. A. El-Mansy, and A. R. Boothroyd, “A general four-terminal charging-current model for the insulated-gate field-ef-fect transistor-1,” Solid-State Electron., vol. 23, no 5, pp. 405–410, May 1980.
11. G. W. Taylor, W. Fichtner, and J. G. Simmons, “A description of MOS internodal capacitances for transient simulation,” IEEE Trans. Computer-Aided Design, vol. CAD-1, pp. 150–156, Oct. 1982.
12. H. K. Gummel and H. C. Poon, “An integral charge control model of bipolar transistors,” Bell Syst. Tech., vol. 49, no. 5, pp. 827– 852, 852, May-June 1970.
13. M. van der Woude, “The calculation of small signal parameters and sensitivities from the spatial analysis of semiconductor devices,’ in Proc. First Int. Conf on the Numerical Analysis of Semiconductor Devices (NASECODE I), Boole Press Limited, Dublin, Ireland, pp. 296-298,1979.
14. S. E. Laux, “Extraction of quasistatic capacitance from numerical device simulation data,” presented at the Joint SIAM-IEEE Conf. Numerical Simulation of VLSI Devices, Boston, MA, Nov. 2–4, 1982.
15. I. L. D'Arcy, E. J. Prendergast, and P. Lloyd, “Modeling of bipolar device structures—physical simulation,” in IEDM Tech. Dig., pp. 516–519, 519, Dec. 1981.
16. J. L. D'Arcy, G. T. Pearman, E. J. Prendergast, and P. Lloyd, “Phys-ical simulation of bipolar device structures,” in Proc. Conf. on Advanced Research in VLSI, Cambridge, MA, pp. 188–200, Jan. 1982.
17. S. E. Laux, “Calculation of quasistatic device behavior with small computational burden,” in Proc. Third Int. Conf. on the Numerical Analysis of Semiconductor Devices and Integrataed Circuits (NASE-CODE CODE III), Boole Press Limited, Dublin, Ireland, pp. 161–166, 1983.
18. J. Machek and W. Fulop, “Harmonic distortion in a one-dimensional p-n-p transistor,” Solid-State Electron., vol. 26, no. 6, pp. 525–536, June 1983.
19. P. M. Chirlian, Integrated and Active Network Analysis and Synthe-sis. Englewood Cliffs, NJ: Prentice-Hall, 1967.
20. D. E. Ward, “Charge-based modeling of capacitance in MOS transistors,” Ph.D. Dissertation, Stanford Univ., Stanford, CA, June 1981.
21. B. M. Grossman and M. J. Hargrove, “Numerical solution of the semiconductor transport equations with current boundary conditions,” IEEE Trans. Electron Devices, vol. ED-30, no. 9, pp. 1092– 1096, 1096, Sept. 1983.
22. S. M. Sze, Physics of Semiconductor Devices, 2nd Ed. New York: Wiley-Interscience, 1981.
23. B. R. Chawla and H. K. Gummel, “Transition region capacitance of diffused p-n junctions,” IEEE Trans. Electron Devices, vol. ED-18, pp. 178–195, Mar. 1971.
24. C. T. Sah, “The equivalent circuit model in solid-state electronics-III: Conduction and displacement currents,” Solid-State Electron., vol. 13, no. 12, pp. 1547–1575, Dec. 1970.
25. S. E. Laux and B. M. Grossman, “A general control-volume formu-lation for modeling impact ionization in semiconductor transport,” this issue, pp. 2076–2082.
26. G. Dahlquist and Å. Björck Numerical Methods, Englewood Cliffs, NJ: Prentice-Hall, 1974.