Reducing processing latency with a heterogeneous FPGA-processor framework

Proceedings - 2014 IEEE 22nd International Symposium on Field-Programmable Custom Computing Machines, FCCM 2014

Volumn , Issue , 2014, Pages 17-20

  Pendlum, Jonathon ^a   Leeser, Miriam ^a   Chowdhury, Kaushik ^a  

^a Northeastern University   (United States)

Author keywords

Cognitive radio; Data latency; FPGA; Heterogeneous computing; Software radio; Spectrum sensing; System on chip

Indexed keywords

COMPUTATION THEORY; COMPUTER ARCHITECTURE; COMPUTER CIRCUITS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); PROGRAMMABLE LOGIC CONTROLLERS; SOFTWARE RADIO; SYSTEM-ON-CHIP;

DATA LATENCIES; HETEROGENEOUS COMPUTING; PARALLEL PROCESSING ARCHITECTURES; PARTITION ALGORITHMS; SEQUENTIAL PROCESSING; SOFTWARE AND HARDWARES; SPECTRUM SENSING; SPECTRUM UTILIZATION;

COGNITIVE RADIO;

EID: 84912551796     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FCCM.2014.13     Document Type: Conference Paper

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