Experiments with gate oxide scaling from 4.5nm down to 2.5nm for boosting CMOS performances

European Solid-State Device Research Conference

Volumn , Issue , 1998, Pages 364-367

  Josse, E ^a   Gowziecki, R ^a   Alieu, J ^a   Mourrain, C ^a   Havond, D ^a   Halimaoui, A ^a   Martin, F ^b   Skotnicki, T ^a  

^a ORANGE LABS   (France)

^b CEA GRENOBLE   (France)

Author keywords

[No Author keywords available]

Indexed keywords

MOSFET DEVICES;

DEVICE RELIABILITY; GATE LEAKAGES; GATE OXIDE; NITRIDED; NMOSFETS; OXIDE SCALING; SUBTHRESHOLD SLOPE;

GATES (TRANSISTOR);

EID: 84908193639     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. C. Hu, IEDM'96 Tech. Dig., pp. 319-322
2. S Jallepalli et al., VLSI'96 Tech. Dig., pp. 138-139
3. P. Bouillon et al., IEDM'97 Tech. Dig. pp. 231-234
4. T. C. Halloway et al., VLSI'97 Tech. Dig., pp. 13-14
5. S. Shim izu et al., VLSI'97 Tech. Dig., pp. 107-108
6. M. Rodder et al., IEDM'97 Tech. Dig. pp. 223-226