A high voltage p-type drain extended MOS in a low voltage sub-micron CMOS technology

European Solid-State Device Research Conference

Volumn , Issue , 1998, Pages 492-495

  Vermandel, Miguel ^a   De Backere, Christof ^a   Van Calster, Andre ^a   Witters, Johan ^b   Tack, Marnix ^b  

^a GHENT UNIVERSITY   (Belgium)

^b LUCENT TECHNOLOGIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MICROELECTRONICS;

CMOS PROCESSS; CMOS TECHNOLOGY; CMOS TRANSISTORS; PROCESS MODIFICATIONS; PROCESS PARAMETERS; PROCESS STEPS; SUB-MICRON CMOS TECHNOLOGY; TCAD SIMULATION;

CMOS INTEGRATED CIRCUITS;

EID: 84907901219     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. B. Jayant Baliga, Trends in Power Semiconductor Devices", IEEE Transactions on Electron devices, October 1996, pp. 1717-1731.
2. J. Van den Steen et al "Technology and circuit aspects of reflective PNLC microdisplays", SID '97, Toronto, September 1197, pp. 195-198.
3. Miguel Vermandel, Christof De Backere, Andre Van Calster, "A High Voltage nDMOS Stmcture in a Standard Sub-micron CMOS process", ESSDERC'97, Editions Frontieres, Stuttgart, 1997, pp. 508-511.
4. J. Haas et all, "High Voltage CMOS LCD Driver using Low Voltage CMOSA Process", CICC'89, 1989, pp. l 4. 6. l-14. 6. 4.
5. Miguel Vermandel, Christof De Backere, Andre Van Calster, "A Simple Mesh Generation Method for Device Simulation of Non-planar MOS Devices", SISPAD '98, submitted for publication.