A high voltage nDMOS structure in a standard sub-micron CMOS process

European Solid-State Device Research Conference

Volumn , Issue , 1997, Pages 508-511

  Vermandel, Miguel ^a   De Backere, Christof ^a   Van Calster, André ^a  

^a GHENT UNIVERSITY   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS PROCESSS; CMOS TECHNOLOGY; CMOS TRANSISTORS; CRITICAL DIMENSION; PROCESS SIMULATORS; PROCESSING STEPS; SIMULATION PROCEDURES; SUBMICRON TECHNOLOGIES;

CMOS INTEGRATED CIRCUITS;

EID: 84907509201     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.1997.194477     Document Type: Conference Paper

References (8)

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8. Andrew S. Grove, Otto Leistiko, JR., and William W. Hooper, Effect of Surface Fields on the Breakdown Voltage of Planar Silicon p-n Junctions, IEEE Transactions on Electron Devices, vol. ED-14, pp 157-162, March 1967