A general model for MOS transistor matching

European Solid-State Device Research Conference

Volumn 13-15 Sept. 1999, Issue , 1999, Pages 464-467

  Croon, J A ^a   Rosmeulen, M ^a   Van Huylenbroeck, S ^a   Decoutere, S ^a  

^a LMEC ^*  (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC RESISTANCE;

CURRENT MATCHING; GENERAL MODEL; MISMATCH PARAMETERS; MODEL PARAMETERS; SERIES RESISTANCES; TRANSISTOR MATCHING;

DRAIN CURRENT;

EID: 84907899112     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. M.J.M. Pelgrom, A.C.J, Duinmaijer, A.P,G, Welbers, Matching Properties of MOS transistors, IEEE Journal of SOIid-state circuits, vol. 24, no. 5, 1989, pp,1433-1440.
2. C,J, Abel, C. Michael, M, Ismail, C.S. Teng, R. Lahri, Characterization of Transistor Mismatch for Statistical CAD of Submicron CMOS Analog Circuits, IEEE International symposium on circuits and systems, 1993, pp. 1401-1404
3. S, Wong, K Pan, D. Ma, A CMOS Mismatch Model and Scaling Effects, IEEE Electron device letters, vol. 18, no, 6, 1997, pp, 261-263.
4. Y. Chen et al., BSIM3v3 Manual, University of California, Berkeley, 1995.
5. J. Bastos, Characterization of MOS Transistor Mismatch for Analog Design, Katholieke Universiteit Leuven, Leuven. 1998