Gate workfunction engineering for deep submicron CMOS

European Solid-State Device Research Conference

Volumn 13-15 Sept. 1999, Issue , 1999, Pages 500-503

  Dachs, C J J ^a   Ponomarev, Y V ^a   Stolk, P A ^a   Montree, A H ^a  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

DEEP SUBMICRON CMOS; DEVICE SIMULATIONS; GATE WORKFUNCTION; GATE WORKFUNCTION ENGINEERING; NMOS TRANSISTORS; OFF-STATE CURRENT; SHORT-CHANNEL EFFECT; TRANSISTOR TYPES;

FIELD EFFECT TRANSISTORS;

EID: 84907891986     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. Y.V. Ponomarev et al, "Gate-Workfiinction Engineering Using Poly-SiGe for High-Perfonnance 0,18J.m CMOS technology ", IEDM'97 Techn. Digest, pp. 829-832.
2. T.-J. King et al, IEDM'90 Techn. Digest, pp 253
3. Y.V. Ponomarev et al, "An Efficient Lateral Profiling of Poly-SiGe-Gated PMOSFET's for O.1J.m CMOS Low-Voltage Applications" to be published VLSI'99.
4. Y. Taur et al, "25nm CMOS Design Considerations", IEDM'98 Techn. Digest, pp. 789-792.
5. H. Matsuhashi et al, "Optimum Electrode Materials for Ta205 Capacitors for High and Low Temperature Processes", Jpn. J. Appl. Phys. Vol. 33 (1994), pp 12931297, March 1994.