Novel parameter extraction techniques for low-voltage, low-power technologies

European Solid-State Device Research Conference

Volumn 13-15 Sept. 1999, Issue , 1999, Pages 452-455

  Minehane, S ^a   McCarthy, K G ^a   O'Sullivan, P ^a   Mathewson, A ^a  

^a UNIVERSITY COLLEGE CORK   (Ireland)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; EXTRACTION; MOSFET DEVICES;

CMOS PROCESSS; DATA POINTS; DEVICE DATA; EXTRACTION TECHNIQUES; LOW-POWER TECHNOLOGY; LOW-VOLTAGE; PARAMETER SET; PMOS FET DEVICES;

PARAMETER EXTRACTION;

EID: 84907887776     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (1)

1. Y. Cheng, M. Jeng, Z. Liu, J. Huang, M. Chan, K. Chen, P.K. Ko and C. Hu, "A Physical and Scalable I-V Model in BSIM3v3 for Analog/Digital Circuit Simulation", IEEE Transactions on Electron Devices 44, pp. 277-287, 1997.