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1
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0035423475
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Ultra-short 25-nm-gate lattice-matched inalasiingaas hemts within the range of 400 ghz cutoff frequency
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Y Yamashita, A. Endoh, K Shinohara, M. Higashiwaki, K. Hikosaka, T. Mimra, S. Hiyamizu, T. Matsui, "Ultra-Short 25-nm-Gate Lattice-Matched InAlAsiInGaAs HEMTs within the Range of 400 GHz Cutoff Frequency", IEEE Electron Device Letters, V01. 22, 2001, pp367-369
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Yamashita, Y.1
Endoh, A.2
Shinohara, K.3
Higashiwaki, M.4
Hikosaka, K.5
Mimra, T.6
Hiyamizu, S.7
Matsui, T.8
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2
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0028274460
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0. 0sum gate inalasiingaas high electron mobility transistor and reduction of its short channel effects
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T. Enoki, M. Tomizawa, Y Umeda, and Y Ishii, ''0. 0Sum Gate InAlAsiInGaAs High Electron Mobility Transistor and reduction of Its Short Channel Effects", Jpn. J. Appl. Phys. Vol 33, 1994,pp798-803
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Enoki, T.1
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3
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0034445433
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First demonstration of ingaadinal as hemts using t-gates fabricated by a bilayer of uviji and pmma resists
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Y. Chen, T. Lodhi, H. McLelland, D. L. Edgar, D. Macintyre, S. Thoms, C. R. Stanley, I. G. Thayne, "First demonstration of InGaAdInAl As HEMTs using T-gates fabricated by a bilayer of UVIJI and PMMA resists", 8th IEEE lntemational Symposium on High Performance Electron Devices for Microwave and Optoelectronic Applications, 2000, pp. 202-205
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(2000)
8th IEEE Lntemational Symposium on High Performance Electron Devices for Microwave and Optoelectronic Applications
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Chen, Y.1
Lodhi, T.2
McLelland, H.3
Edgar, D.L.4
Macintyre, D.5
Thoms, S.6
Stanley, C.R.7
Thayne, I.G.8
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4
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0040708838
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Electron beam lithography process for t-and r-shaped gate fabrication using chemically amplified duv resists and pmma
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Y Chen, D. Macintyre, S. Thoms, "Electron beam lithography process for T-and r-shaped gate fabrication using chemically amplified DUV resists and PMMA", J. Vac. Sci. Technology, B17, 1999, pp. 2507-2511
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Chen, Y.1
Macintyre, D.2
Thoms, S.3
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5
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0038020948
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Novel high uniformity highly reproducible non selective wet digital gate recess etch process for inp hemts
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Accept for publication
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Xin Cao, lain Thayne, "Novel high uniformity highly reproducible non selective wet digital gate recess etch process for InP HEMTs", Microelectronic Engineering, 2003, Accept for publication.
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(2003)
Microelectronic Engineering
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Cao, X.1
Thayne, I.2
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