An energy-efficient parallel-processing method based on master-hibernating DVFS

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2014, Pages 1724-1727

  Hamamoto, Masaki ^a   Yamaoka, Masanao ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ENERGY UTILIZATION; VOLTAGE SCALING;

AGGRESSIVE VOLTAGE SCALING; CONVENTIONAL METHODS; ENERGY EFFICIENT; K-MEANS CLUSTERING;

ENERGY EFFICIENCY;

EID: 84907383789     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2014.6865487     Document Type: Conference Paper

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