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Volumn , Issue , 2014, Pages

A new seven level symmetric inverter with reduced number of switches and DC sources

Author keywords

Multilevel inverters; PWM technique; Total harmonic distortion

Indexed keywords

ELECTRICAL ENGINEERING; FAST FOURIER TRANSFORMS; TOPOLOGY;

EID: 84904152547     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICAEE.2014.6838484     Document Type: Conference Paper
Times cited : (6)

References (14)
  • 1
    • 59749098725 scopus 로고    scopus 로고
    • A cascade multilevel converter topology with reduced number of switches
    • Ebrahim Babaei, "A Cascade Multilevel Converter Topology With Reduced Number of Switches", IEEE Trans. on Power electronics, Vol.23, No. 6, pp. 2657-2664, 2008G.
    • (2008) IEEE Trans. on Power Electronics , vol.23 , Issue.6 , pp. 2657-2664
    • Babaei, E.1
  • 3
    • 84879495556 scopus 로고    scopus 로고
    • Analysis of thd and output voltage performance for cmli using carrier pwm
    • P. Palanivel, S.S. Dash, "Analysis of THD and output voltage performance for CMLI using carrier PWM", IET Power Electronics, 2011.
    • (2011) IET Power Electronics
    • Palanivel, P.1    Dash, S.S.2
  • 4
    • 84862849349 scopus 로고    scopus 로고
    • Symmetric multilevel inverters with reduced components based on non isolated dc sources
    • M.F. Kangarlu, E. Babaei, S, Laali, "Symmetric multilevel inverters with reduced components based on non isolated dc sources", IET Power Electron., 2012, Vol.5, pp. 571-581.
    • (2012) IET Power Electron , vol.5 , pp. 571-581
    • Kangarlu, M.F.1    Babaei, E.2    Laali, S.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.