Cascaded seven level inverter with reduced number of switches using level shifting PWM technique

Proceedings of 2013 International Conference on Power, Energy and Control, ICPEC 2013

Volumn , Issue , 2013, Pages 676-680

  Lakshmi, T V V S ^a   George, Noby ^a   Umashankar, S ^a   Kothari, D P ^b  

^a VIT UNIVERSITY   (India)

^b J B Group of Institutions   (India)

Author keywords

multilevel inverter; PWM Techniques; Total Harmonic Distortion

Indexed keywords

CASCADED MULTI-LEVEL INVERTERS; GATE DRIVE CIRCUITRY; HIGH POWER APPLICATIONS; MULTILEVEL INVERTER; NUMBER OF SWITCHES; POWER ELECTRONIC DEVICES; PWM TECHNIQUES; TOTAL HARMONIC DISTORTION (THD);

ELECTRIC POWER SYSTEMS; TOPOLOGY; WAVE FILTERS;

TIME SWITCHES;

EID: 84880884736     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICPEC.2013.6527742     Document Type: Conference Paper

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