A new predistortion architecture with sampling clock jitter mitigation for wideband systems

Proceedings - IEEE Global Communications Conference, GLOBECOM

Volumn , Issue , 2013, Pages 3241-3246

  Liu, Ying ^a   Pan, Wensheng ^a   Shao, Shihai ^a   Tang, Youxi ^a  

^a UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA   (China)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURE; BROADBAND NETWORKS; FEEDBACK LINEARIZATION; MEAN SQUARE ERROR; SIGNAL TO NOISE RATIO;

CLOCK JITTERS; DIGITAL PREDISTORTION; FEEDBACK PATHS; JITTER MITIGATION; NONIDEAL; PERFORMANCE; PREDISTORTIONS; SAMPLING CLOCK JITTER; SAMPLING CLOCKS; WIDEBAND SYSTEMS;

CLOCKS;

EID: 84904106378     PISSN: 23340983     EISSN: 25766813     Source Type: Conference Proceeding    
DOI: 10.1109/GLOCOM.2013.6831571     Document Type: Conference Paper

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