A multi banked - Multi ported - Non blocking shared L2 cache for MPSoC platforms

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2014, Pages

  Loi, Igor ^a   Benini, Luca ^a,b  

^a UNIVERSITY OF BOLOGNA   (Italy)

^b ETH ZURICH   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

AGGREGATES; CACHE MEMORY; COMPUTER ARCHITECTURE; DESIGN; HIERARCHICAL SYSTEMS; SILICON ON INSULATOR TECHNOLOGY; SYSTEM-ON-CHIP;

EMBEDDED APPLICATION; HIERARCHICAL CLUSTERS; INTER-CORE COMMUNICATIONS; LASTLEVEL CACHES (LLC); NOVEL ARCHITECTURE; ON-CHIP L2 CACHE; PARALLEL COMPUTING SYSTEM; STRINGENT REQUIREMENT;

MICROPROCESSOR CHIPS;

EID: 84903822575     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.7873/DATE2014.093     Document Type: Conference Paper

References (13)

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