Why on-chip cache coherence is here to stay

Communications of the ACM

Volumn 55, Issue 7, 2012, Pages 78-89

  Martin, Milo M K ^a   Hill, Mark D ^b   Sorin, Daniel J ^c  

^a UNIVERSITY OF PENNSYLVANIA   (United States)

^b UNIVERSITY OF WISCONSIN MADISON   (United States)

^c DUKE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE COHERENCE; CACHE COHERENCE PROTOCOLS; COHERENCE STATE; ON CHIPS; ON-CHIP CACHE; REQUEST MESSAGES; SHARED CACHE;

COMPUTER APPLICATIONS; COMPUTER SCIENCE;

HARDWARE;

EID: 84863758078     PISSN: 00010782     EISSN: 15577317     Source Type: Journal    
DOI: 10.1145/2209249.2209269     Document Type: Article

References (19)

1. th Annual International Symposium on Computer Architecture (Honolulu, May). IEEE Computer Society Press, Los Alamitos, CA, 1988, 280-298.
2. Boyd-Wickizer, S. Clements, A.T., Mao, Y., Pesterev, A., Kaashoek, M.F., Morris, R., and Zeldovich, N. An analysis of Linux scalability to many cores. In Proceedings of the Ninth USENIX Symposium on Operating Systems Design and Implementation (Vancouver, Oct. 4-6). USENIX Association, Berkeley, CA, 2010, 1-8.
3. Bryant, R. Scaling Linux to the extreme. In Proceedings of the Linux Symposium (Boston, June 27-July 2, 2004), 133-148.
4. Butler, M., Barnes, L., Sarma, D.D., and Gelinas, B. Bulldozer: An approach to multithreaded compute performance. IEEE Micro 31, 2 (Mar./Apr. 2011), 6-15.
5. th International Conference on Parallel Architectures and Compilation Techniques (Galveston Island, TX, Oct. 10-14). IEEE Computer Society, Washington, D.C., 2011, 155-166.
6. Conway, P., Kalyanasundharam, N., Donley, G., Lepak, K., and Hughes, B. Cache hierarchy and memory subsystem of the AMD Opteron processor. IEEE Micro 30, 2 (Mar./Apr. 2010), 16-29.
7. th Symposium on High-Performance Computer Architecture (San Antonio, TX, Feb. 12-16). IEEE Computer Society, Washington, D.C., 2011, 169-180.
8. Hill, M.D., Larus, J.R., Reinhardt, S.K., and Wood, D.A. Cooperative shared memory: Software and hardware for scalable multiprocessors. ACM Transactions on Computer Systems 11, 4 (Nov. 1993), 300-318.
9. Hill, M.D. and Smith, A.J. Evaluating associativity in CPU caches. IEEE Transactions on Computers 38, 12 (Dec. 1989), 1612-1630.
10. Howard, J. et al. A 48-core IA-32 message-passing processor with DV FS in 45nm CMOS. In Proceedings of the International Solid-State Circuits Conference (San Francisco, Feb. 7-11, 2010), 108-109.
11. rd Annual IEEE/ACM International Symposium on Microarchitecture (Atlanta, Dec. 4-8). IEEE Computer Society, Washington, D.C., 2010, 151-162.
12. th Annual International Symposium on Computer Architecture (Austin, TX, June 20-24). ACM Press, New York, 2009, 140-151.
13. Kelm, J.H., Johnson, D.R., Tuohy, W., Lumetta, S.S., and Patel, S.J. Cohesion: An adaptive hybrid memory model for accelerators. IEEE Micro 31, 1 (Jan./Feb. 2011), 42-55.
14. th Annual International Symposium on Computer Architecture (Denver, June 2-4). ACM Press, New York, 1997, 241-251.
15. Nickolls, J. and Dally, W.J. The GPU computing era. IEEE Micro 30, 2 (Mar./Apr. 2010), 56-69.
16. Shah, M., Barren, J., Brooks, J., Golla, R., Grohoski, G., Gura, N., Hetherington, R., Jordan, P., Luttrell, M., Olson, C., Sana, B., Sheahan, D., Spracklen, L., and Wynn, W. UltraSPARC T2: A highly treaded, powerefficient SPARC SOC. In Proceedings of the IEEE Asian Solid-State Circuits Conference (Jeju, Korea, Nov. 12-14, 2007), 22-25.
17. Singhal, R. Inside Intel next-generation Nehalem microarchitecture. Hot Chips 20 (Stanford, CA, Aug. 24-26, 2008).
18. Sorin, D.J., Hill, M.D., and Wood, D.A. A Primer on Memory Consistency and Cache Coherence. Morgan & Claypool Publishers, 2011.
19. rd Annual IEEE/ACM International Symposium on Microarchitecture (Atlanta, Dec. 4-8). IEEE Computer Society, Washington, D.C., 2010, 471-482.