Formal proof and test case generation for critical embedded systems using SCADE

IFIP Advances in Information and Communication Technology

Volumn 156, Issue , 2004, Pages 499-504

  Durrieu, Guy ^b   Laurent, Odile ^a   Seguin, Christel ^b   Wiels, Virginie ^b  

^a AIRBUS   (France)

^b ONERA   (France)

Author keywords

Critical embedded systems; Formal techniques; Test generation; Verification

Indexed keywords

INFORMATION TECHNOLOGY; VERIFICATION;

AUTOMATIC TEST GENERATION; AVIONICS SYSTEMS; FORMAL PROOFS; FORMAL TECHNIQUES; TEST CASE GENERATION; TEST GENERATIONS;

EMBEDDED SYSTEMS;

EID: 84902465828     PISSN: 18684238     EISSN: None     Source Type: Book Series    
DOI: 10.1007/978-1-4020-8157-6_44     Document Type: Conference Paper

References (3)

1. O. Laurent, P. Michel, V. Wiels. Using formal verification techniques to reduce simulation and test effort. FME 2001. LNCS 2021, Jose Nuno Oliveira and Pamela Zave eds. Springer Verlag.
2. A. Lakehal, I. Parissis, L. du Bousquet. Critères de couverture structurelle de programmes Lustre. Proceedings of AFADL 04.
3. th international conference on Automated Software Engineering (ASE) 2000.