Validation of railway interlocking systems by formal verification, a case study

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 8368 LNCS, Issue , 2014, Pages 237-252

  Bonacchi, Andrea ^a   Fantechi, Alessandro ^a   Bacherini, Stefano ^b   Tempestini, Matteo ^b   Cipriani, Leonardo ^b  

^a UNIVERSITY OF FLORENCE   (Italy)

^b General Electric Transportation Systems   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

INDUSTRIAL APPLICATIONS; INTERLOCKING SIGNALS; MODEL CHECKING;

AUTOMATIC VERIFICATION; FORMAL VERIFICATIONS; INDUSTRIAL PARTNERS; INHERENT COMPLEXITY; INTERLOCKING SYSTEMS; LARGE AMOUNTS; RAILWAY INTERLOCKING SYSTEM; STATE-SPACE EXPLOSION;

SOFTWARE ENGINEERING;

EID: 84901679288     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-319-05032-4_18     Document Type: Conference Paper

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