A formal verification environment for railway signaling system design

Formal Methods in System Design

Volumn 12, Issue 2, 1998, Pages 139-161

  Bernardeschi, Cinzia ^a   Fantechi, Alessandro ^b   Gnesi, Stefania ^c   Larosa, Salvatore ^c   Mongardi, Giorgio ^d   Romano, Dario ^d  

^a UNIVERSITY OF PISA   (Italy)

^b UNIVERSITY OF FLORENCE   (Italy)

^c ISTI CNR   (Italy)

^d ANSALDO ENERGIA   (Italy)

Author keywords

Mechanical verification; Model checking; Safety critical systems; Temporal logic

Indexed keywords

ALGEBRA; ALGORITHMS; COMPUTER CONTROL SYSTEMS; COMPUTER SOFTWARE; EMBEDDED SYSTEMS; RAILROAD TRANSPORTATION; REAL TIME SYSTEMS; SECURITY SYSTEMS; THEOREM PROVING; ACCIDENT PREVENTION; COMPUTER CONTROL; CONTROL SYSTEMS; INTERLOCKING SIGNALS; RAILROAD ACCIDENTS;

MECHANICAL VERIFICATIONS; MODEL CHECKING; SAFETY CRITICAL SYSTEMS; TEMPORAL LOGIC; SOFTWARE PACKAGE JACK;

SYSTEMS ANALYSIS; COMPUTER AIDED LOGIC DESIGN;

EID: 0032027829     PISSN: 09259856     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1008645826258     Document Type: Conference Paper

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