Modeling of re-sputtering induced bridge of tungsten bit-lines for NAND flash memory cell with 37nm node technology

2007 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2007

Volumn , Issue , 2007, Pages 45-48

  Hwang, Byungjoon ^a   Lee, Yero ^a   Min, Jeong Guk ^a   Shin, Hwakyung ^a   Lim, Namsu ^a   Kim, Sungjin ^a   Chung, Won Young ^a   Kim, Tai Kyung ^a   Park, Jang Ho ^a   Lee, Yun Kyoung ^a   Kwak, Donghwa ^a   Park, Jaekwan ^a   Lee, Won Seong ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

LOW-K DIELECTRIC; MEMORY ARCHITECTURE; NAND CIRCUITS; SEMICONDUCTOR DEVICES; SILICA; SPUTTERING; THRESHOLD VOLTAGE;

ELECTRICAL ISOLATION; HIGH DENSITY FLASH MEMORY; MICRO-BRIDGE; NAND FLASH MEMORY; NODE TECHNOLOGY; PROCESS FACTOR; RE-SPUTTERING; THRESHOLD VOLTAGE SHIFTS;

FLASH MEMORY;

EID: 84901355558     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1007/978-3-211-72861-1_11     Document Type: Conference Paper

References (3)

1. Kinam Kim et al., "Future Outlook of NAND Flash Technology for 40nm Node and Beyond". IEEE NVSMW, pp. 9-11. 2006.
2. Jung-Dai Choi et al., "A 0.15 um NAND Flash Technology with 0.11um2 Cell Size for 1 Gbit Flash Memory", IEDM. pp. 767-770. 2000.
3. Won-Young Chung et al., "Integrated Simulation of Equipment and Topography for Plasma Etching in the DRM Reactor". SISPAD. pp. 127-130. 2000.