Hardware-accelerated regular expression matching for high-throughput text analytics

2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 - Proceedings

Volumn , Issue , 2013, Pages

  Atasu, Kubilay ^a   Polig, Raphael ^a   Hagleitner, Christoph ^a   Reiss, Frederick R ^b  

^a IBM RESEARCH ZURICH   (Switzerland)

^b IBM RESEARCH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); NETWORK ARCHITECTURE; PROGRAM COMPILERS; RECONFIGURABLE ARCHITECTURES;

HARDWARE-ACCELERATED; NONDETERMINISTIC STATE; NOVEL ARCHITECTURE; RECONFIGURABLE LOGIC; REGULAR EXPRESSIONS; REGULAR-EXPRESSION MATCHING; RELATIONAL ALGEBRA; THROUGHPUT RATE;

PATTERN MATCHING;

EID: 84898605818     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2013.6645534     Document Type: Conference Paper

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