A 0.75-million-point fourier-transform chip for frequency-sparse signals

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 57, Issue , 2014, Pages 458-459

  Abari, Omid ^a   Hamed, Ezz ^a   Hassanieh, Haitham ^a   Agarwal, Abhinav ^a   Katabi, Dina ^a   Chandrakasan, Anantha P ^a   Stojanovic, Vladimir ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FAST FOURIER TRANSFORMS; PATTERN MATCHING;

FFT/IFFT; HIGH POWER CONSUMPTION; LONG CODES; RADAR SIGNAL PROCESSING; SILICON AREA; SPARSE SIGNALS; SPECTRUM SENSING;

SIGNAL PROCESSING;

EID: 84898074091     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2014.6757512     Document Type: Conference Paper

References (6)

1. H. Hassanieh, et al., "Simple and Practical Algorithm for Sparse Fourier Transform," ACM Symp. Discrete Algorithms, pp. 1183-1184, 2012.
2. G. Zhong, et al., "A Power-Scalable Reconfigurable FFT/IFFT IC Based on a Multi-Processor Ring," IEEE J. Solid-State Circuits, vol. 41, no. 2, pp. 483-495, 2006.
3. M. Seok, et al., "A 0.27V 30MHz 17.7nJ/transform 1024-pt Complex FFT Core with Super-Pipelining," ISSCC Dig. Tech Papers, pp. 342-344, 2011.
4. Y. Chen, et al., "A 2.4-Gsample/s DVFS FFT Processor for MIMO OFDM Communication Systems," IEEE J. Solid-State Circuits, vol. 43, no. 5, pp. 1260-1273, 2008.
5. C. Yang, et al., "Power and Area Minimization of Reconfigurable FFT Processors: A 3GPP-LTE Example," IEEE J. Solid-State Circuits, vol. 47, no. 3, pp. 757-768, 2012.
6. sFFT C++ code. http://groups.csail.mit.edu/netmit/sFFT/code.html