Normally-off computing project: Challenges and opportunities

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2014, Pages 1-5

  Nakamura, Hiroshi ^a   Nakada, Takashi ^a   Miwa, Shinobu ^a  

^a UNIVERSITY OF TOKYO   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTING PROJECTS; NON-VOLATILE MEMORY; NORMALLY OFF; POWER GATINGS; POWER REDUCTIONS; VOLATILE MEMORY;

COMPUTER AIDED DESIGN;

EID: 84897878703     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2014.6742850     Document Type: Conference Paper

References (4)

1. R. Puri, L. Stok, and S. Bhattacharya, "Keeping hot chips cool", in Proceeding of the 42nd annual Design Automation Conference (dac), pp. 285-288, June 2005
2. L. Zhao, D. Ikebuchi, T. Saito, M. Kamata, N. Seki, Y. Kojima, H. Amano, S. Koyama, T. Hashida, Y. Umahashi, D. Masuda, K. Usami, K. Kimura, M. Namiki, S. Takeda, H. Nakamura, M. Kondo, "Geyser-2: The second prototype cpu with fine-grained run-time power gating", in Proceeding of 16th Asia and South Pacific Design Automation Conference (aspdac), pp. 87-88, Jan. 2011
3. K. Usami, M. Kudo, K. Matsunaga, T. Kosaka, Y. Tsurui, W. Wang, H. Amano, H. Kobayashi, R. Sakamoto, M. Namiki, M. Kondo, H. Nakamura, "Design and Control Methodology for Fine Grain Power Gating based on Energy Characterization and Code Profiling of Microprocessors", in Proceeding of 19th Asia and South Pacific Design Automation Conference (asp-dac), Jan. 2014
4. "Normally-Off Computing Project": http://noff-pj.jp/en