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Volumn 3, Issue , 2003, Pages 1349-1352

Bias circuit topologies for minimization of RF amplifier memory effects

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; ELECTRIC NETWORK TOPOLOGY; FREQUENCY RESPONSE;

EID: 84897514291     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EUMC.2003.177737     Document Type: Conference Paper
Times cited : (9)

References (2)
  • 1
    • 0024934557 scopus 로고
    • Measurement and simulation of memory effects in predistortion linearisers
    • December
    • Bosch W., Gatti G., "Measurement and Simulation of Memory Effects in Predistortion Linearisers", IEEE trans. On MTT, Vol. 37, No. 12, pp. 1885-1890, December 1989.
    • (1989) IEEE Trans. on MTT , vol.37 , Issue.12 , pp. 1885-1890
    • Bosch, W.1    Gatti, G.2
  • 2
    • 0035416329 scopus 로고    scopus 로고
    • Measurement technique for characterizing memory effects in RF power amplifiers
    • August
    • Vuolevi J.H.K. et al, "Measurement Technique for Characterizing Memory Effects in RF Power Amplifiers" IEEE Trans. On MTT, Vol. 30 No. 8, 1383-1389, August 2001.
    • (2001) IEEE Trans. on MTT , vol.30 , Issue.8 , pp. 1383-1389
    • Vuolevi, J.H.K.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.